ATMEGA16-16AU SL602 Atmel, ATMEGA16-16AU SL602 Datasheet - Page 146

• Manufacturer Part Number: ATMEGA16-16AU SL602
• Manufacturer: Atmel

Internal Clock
Generation – The
Baud Rate Generator
2466T–AVR–07/10
Figure 70. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous Master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 60
the UBRR value for each mode of operation using an internally generated clock source.
txclk
rxclk
xcki
xcko
fosc
DDR_XCK
XCK
Pin
contains equations for calculating the baud rate (in bits per second) and for calculating
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (Internal Signal). Used for synchronous Slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous Master
operation.
XTAL pin frequency (System Clock).
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
Figure
/ 4
70.
/ 2
DDR_XCK
ATmega16(L)
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
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