ATAM894R-TNSY Atmel, ATAM894R-TNSY Datasheet - Page 82
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ATAM894R-TNSY
Manufacturer Part Number
ATAM894R-TNSY
Description
flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
Manufacturer
Atmel
Datasheet
1.ATAM894R-TNSY.pdf
(97 pages)
- Current page: 82 of 97
- Download datasheet (2Mb)
Figure 6-64. Burst Modulation 2
82
Counter 2/2
Counter 3
ATAM894
CM31
CM32
TOG3
TOG2
CL3
T3O
M3
SO
0 1 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 1 0 1
3
0
Combination Mode 12: Burst Modulation 2
SSI mode 1:
Timer 2 output mode 2:
Timer 2 output mode 1/6:
Timer 3 mode 7:
The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare
mode registers must be programmed to generate the carrier frequency with the output toggle
flip-flop (M3). The internal data output (SO) of the SSI is used to enable and disable the Timer 3
output. The SSI can be supplied with the toggle signal of Timer 2.
Combination Mode 13: FSK Modulation
SSI mode 1:
Timer 2 output mode 3:
Timer 2 output mode 1/6:
Timer 3 mode 8:
The two compare registers are used to generate two different time intervals. The SSI data output
selects which compare register is used for the output frequency generation. A '0' level at the SSI
data output enables the compare register 1 and a '1' level enables the compare register 2. The
compare- and compare mode registers must be programmed to generate the two frequencies
via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2 or any
other clock source. The Timer 3 counter is driven by an internal or external clock source.
1
2
3
5 0 1 0 1
5 0 1 0 1
8-bit shift register internal data output (SO) to the Timer 3
8-bit compare counter and 4-bit prescaler
Timer 2 compare match toggles (TOG2) to the SSI
Carrier frequency burst modulation controlled by the internal
output (SO) of SSI
8-bit shift register internal data output (SO) to the Timer 3
8-bit compare counter and 4-bit prescaler
Timer 2 4-bit compare match signal (POUT) to the SSI
FSK modulation with shift register data output (SO)
5 0 1 0 1
5 0 1 0 1
3
5 0 1 0 1
0
5 0 1 0 1
1
5 0 1 0 1
2
5 0 1 0 1
3
4679D–4BMCU–05/05
5 0 1 0 1
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