ATAM894R-TNSY Atmel, ATAM894R-TNSY Datasheet - Page 28
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ATAM894R-TNSY
Manufacturer Part Number
ATAM894R-TNSY
Description
flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
Manufacturer
Atmel
Datasheet
1.ATAM894R-TNSY.pdf
(97 pages)
- Current page: 28 of 97
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6.2.3.1
6.2.3.2
Table 6-3.
6.2.4
28
Auxiliary Address: '5'hex First Write Cycle
3 2 1 0
x x 1 1
x x 0 1
x x 1 0
x x 0 0
1 1 x x
0 1 x x
1 0 x x
0 0 x x
Code
ATAM894
Function
BP50 in input mode – interrupt disabled
BP50 in input mode – rising edge interrupt
BP50 in input mode – falling edge interrupt
BP50 in output mode – interrupt disabled
BP51 in input mode – interrupt disabled
BP51 in input mode – rising edge interrupt
BP51 in input mode – falling edge interrupt
BP51 in output mode – interrupt disabled
Bi-directional Port 4
Port 5 Data Register (P5DAT)
Port 5 Control Register (P5CR) Byte Write
Port 5 Control Register
P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code
The bi-directional Port 4 is a bit-wise configurable I/O port and provides the external pins for the
Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the
same way as bi-directional Port 2 (see
data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI).
The I/O pins for the SC and SD lines have an additional mode to generate an SSI-interrupt.
All four Port 4 pins can be individually switched by the P4CR register.
shows the internal interfaces to bi-directional Port 4.
P5DAT
P5CR
First write cycle
Second write
cycle
Bit 3
P5DAT3
Bit 2
P5DAT2
Bit 3
P51M2
Bit 7
P53M2
Second Write Cycle
3 2 1 0
x x 1 1
x x 0 1
x x 1 0
x x 0 0
1 1 x x
0 1 x x
1 0 x x
0 0 x x
Code
Figure 6-3 on page
Bit 2
P51M1
Bit 6
P53M1
Bit 1
P5DAT1
BP52 in output mode – interrupt disabled
Function
BP52 in input mode – interrupt disabled
BP52 in input mode – rising edge interrupt
BP52 in input mode – falling edge interrupt
BP53 in input mode – interrupt disabled
BP53 in input mode – rising edge interrupt
BP53 in input mode – falling edge interrupt
BP53 in output mode – interrupt disabled
Bit 1
P50M2
Bit 5
P52M2
Primary register address: '5'hex
Bit 0
P5DAT0
26). Two additional multiplexes allow
Auxiliary register address: '5'hex
Bit 0
P50M1
Bit 4
P52M1
Reset value: 1111b
Reset value: 1111b
Reset value: 1111b
Figure 6-6 on page 29
4679D–4BMCU–05/05
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