ATAM894R-TNSY Atmel, ATAM894R-TNSY Datasheet - Page 47
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ATAM894R-TNSY
Manufacturer Part Number
ATAM894R-TNSY
Description
flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
Manufacturer
Atmel
Datasheet
1.ATAM894R-TNSY.pdf
(97 pages)
- Current page: 47 of 97
- Download datasheet (2Mb)
6.3.3
6.3.3.1
Figure 6-24. Timer 3
4679D–4BMCU–05/05
T3I
Timer 3
T1OUT
SYSCL
POUT
T3EX
Features
T3CS
CL3
RES
Compare 3/1
Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The
timer can be used as event counter, timer and signal generator. Its output can be programmed
as modulator and demodulator for the serial interface. The two compare registers enable various
modes of signal generation, modulation and demodulation. The counter can be driven by inter-
nal and external clock sources. For external clock sources, it has a programmable edge-
sensitive input which can be used as counter input, capture signal input or trigger input. This
timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core
capture register while it is running. In capture mode, the counter value can be captured by a pro-
grammable capture event from the Timer 3 input or Timer 2 output.
T3CO1
• Two Compare Registers
• Capture Register
• Edge Sensitive Input with Zero Cross Detection Capability
• Trigger and Single Action Modes
• Output Control Modes
• Automatic Modulation and Demodulation Modes
• FSK Modulation
• Pulse width Modulation (PWM)
• Manchester Demodulation Together with SSI
• Bi-phase Demodulation Together with SSI
• Pulse-width Demodulation Together with SSI
sleep and OSC-Stop
8-bit Counter 3
T3CP
Compare 3/2
T3CO2
CP3
I/O-bus
I/O-bus
yes), this timer input is stopped too. The counter is readable via its
T3CM1
T3C
Control
T3CM2
T3ST
TOG2
Timer 2
T3M
Control
T3EX
T3I
CM31
RES
INT5
SO
M2
TOG3
SSI
Modulator 3
Demodu-
lator 3
ATAM894
SCI
SI
SSI
T3O
47
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