ATAM894R-TNSY Atmel, ATAM894R-TNSY Datasheet - Page 60
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ATAM894R-TNSY
Manufacturer Part Number
ATAM894R-TNSY
Description
flash, Microcontrollers, Microprocessors, Semiconductors and Actives, ic, mcu
Manufacturer
Atmel
Datasheet
1.ATAM894R-TNSY.pdf
(97 pages)
- Current page: 60 of 97
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6.3.4
6.3.4.1
6.3.4.2
60
ATAM894
Synchronous Serial Interface (SSI)
SSI Features
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either for serial communication with external
devices such as EEPROMs, shift registers, display drivers, other microcontrollers, or as a
means for generating and capturing on-chip serial streams of data. External data communication
takes place via the Port 4 (BP4), a multi-functional port which can be software configured by
writing the appropriate control word into the P4CR register. The SSI can be configured in any of
the following ways:
• 2- and 3-wire NRZ
• 2-wire mode (MCL compatible), additional internal 2-wire link for multi-chip packaging
• With Timer 2
• With Timer 3
1. 2-wire external interface for bi-directional data communication with one data terminal
2. 3-wire external interface for simultaneous input and output of serial data, with a serial
3. Timer/SSI combined modes - the SSI used together with Timer 2 or Timer 3 is capable
4. Multi-chip link (MCL) – the SSI can also be used as an interchip data interface for use in
solutions
– Bi-phase modulation
– Manchester modulation
– Pulse-width demodulation
– Burst modulation
– Pulse-width modulation (PWM)
– FSK modulation
– Bi-phase demodulation
– Manchester demodulation
– Pulse-width demodulation
– Pulse position Demodulation
and one shift clock. The SSI uses the Port BP43 as a bi-directional serial data line (SD)
and BP40 as shift clock line (SC).
input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The
SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43
(configured in P4CR as input!). Serial output data (SO) in this case is passed through to
BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in
mode 6).
of performing a variety of data modulation and demodulation functions (see section
“Timer”). The modulating data is converted by the SSI into a continuous serial stream of
data which is in turn modulated in one of the timer functional blocks. Serial demodu-
lated data can be serially captured in the SSI and read by the controller. In the Timer 3
modes 10 and 11 (demodulation modes) the SSI can only be used as demodulator.
single package multi-chip modules or hybrids. For such applications, the SSI is pro-
vided with two dedicated pads (MCL_SD and MCL_SC) which act as a two-wire chip-
to-chip link. The MCL can be activated by the MCL control bit. Should these MCL pads
be used by the SSI, the standard SD and SC pins are not required and the correspond-
ing Port 4 ports are available as conventional data ports.
4679D–4BMCU–05/05
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