ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 6

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Change Summary
The following table captures the changes from the April 2005 issue.
The following table captures the changes from the July 2004 issue.
Page
Page
24
25
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26
12
48
49
50
51
52
53
54
54
56
56
11
8.4.1, “Read Cycle“
Figure 6 "Read Cycle Operation"
8.4.2, “Write Cycle“
Figure 7 "Write Cycle Operation"
"Pin Description" - CKo0-3
"Pin Description" - DTA, WAIT
“AC Electrical Characteristics1 - FPi0-2
and CKi0-2 Timing“
Figure 9 "Frame Skew Timing Diagram"
(1) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (65.536 MHz)
Timing“
(2) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (32.768 MHz)
Timing“
(3) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (16.384 MHz)
Timing“
(4) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (8.192 MHz)
Timing“
“AC Electrical Characteristics - Output
Clock Jitter Generation“
“AC Electrical Characteristics - Serial
Data Timing to CKi“
Figure 12 "Serial Data Timing to CKi"
“AC Electrical Characteristics - Serial
Data Timing to CKo“
Figure 13 "Serial Data Timing to CKo"
“AC Electrical Characteristics - CKo to
Other CKo 1Skew“
Figure 14 "CKo to other CKo Skew"
Item
Item
Zarlink Semiconductor Inc.
ZL50074
Clarified WAIT signal description in Read Cycle.
Corrected WAIT signal tristate timing in Read Cycle.
Clarified WAIT signal description in Write Cycle.
Corrected WAIT signal tristate timing in Write Cycle.
Added special requirement for using output clock at
65.536 MHz.
Added more detailed description to the DTA and WAIT
pins.
Added t
maximum values.
Added FPi1,2 frame pulse to Figure “Frame Skew Timing
Diagram” to clarify frame boundary skew.
Added CKO0-3 and FPO0-3 setup and hold parameters for
all different clock rates.
Added this table to specify CKO0-3 jitter generation.
(1) Values of parameters t
t
(2) Separated parameter t
Added more detail to figure.
Values of parameters t
t
Added more detail to figure.
Added CKO skew parameters, t
internal APLL).
Added figure to show t
SINV,
SONV,
6
t
SIPZ
t
SOPZ
FPIS
and t
, t
and t
FPIH
SINZ
SONZ
(input frame pulse setup and hold)
are revised.
SOPS,
CKOS.
are revised.
Change
Change
SIPS,
CKD
t
SOPH,
into t
t
SIPH,
CKOS
CKDP
t
SONS,
t
, (clock source to
SINS,
and t
t
SONH,
t
SINH,
CKDN.
Data Sheet
t
t
SIPV,
SOPV,