ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 29

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.0
The memory map for the ZL50074 is given in Table 11.
12.0
This section describes all the memories and registers that are used in this device.
12.1
Address range 00000 - 1FFFF hex.
On power-up, all Connection Memory locations are initialized automatically to 00000000
Initialization feature, as described in Section 12.6 and Section 12.7.
The 32 bit Connection Memory has 32,768 locations. Each 32 bit long-word is used to program the desired source
data and any other per-channel characteristics of one output time-slot.
The memory map for the Connection Memory is sub-divided into 32 blocks, each corresponding to one of the
possible 32 output stream group numbers. The address ranges for these blocks are illustrated in Table 12.
Table 11 - Memory Map
Address (Hex)
00000 - 1FFFF
28000 - 2FFFF
4028C - 4028F
40294 - 7FFFF
20000 - 27FFF
30000 - 401FF
40288 - 4028B
40200 - 4027F
40280 - 40283
40284 - 40287
40290 - 40293
Connection Memory
Memory Map of ZL50074
Detailed Memory and Register Descriptions
Connection Memory
Connection Memory LSB
Data Memory: Read only; Bus error on write (BERR)
Invalid Address. Access causes Bus error (BERR)
Group Control Registers
Input Clock Control Register
Output Clock Control Register
Block Init Register
Block Init Enable
Global Rate Control Register
Invalid Address. Access causes Bus error (BERR)
Zarlink Semiconductor Inc.
ZL50074
29
Description
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, using the Block
Data Sheet