ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 13

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
1.0
1.1
The device has 128 ST-BUS/GCI-Bus inputs (STiA0 - 31, STiB0 - 31, STiC0 - 31, STiD0 - 31) and 128
ST-BUS/GCI-Bus outputs (SToA0 - 31, SToB0 - 31, SToC0 - 31, SToD0 - 31). It is a non-blocking digital switch with
32,768 64 kbps channels and is capable of operating at 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps.
The inputs accept serial data streams and the outputs deliver serial data streams at one of these data rates. All
input and output streams operate at the same rate. There are 32 input groups with each group consisting of 4
streams (‘A’, ‘B’, ‘C’ and ‘D’). If the data rate is set to 16.384 Mbps or 8.192 Mbps, STiA0 - 31, STiB0 - 31, STiC0 -
31 and STiD0 - 31 are used for the input traffic. When the data rate is set to 32.768 Mbps, STiA0 - 31 and STiB0 -
31 are used for the input traffic; STiC0 - 31 and STiD0 - 31 are not used. When the data rate is set to 65.536 Mbps,
STiA0 - 31 are used for the input traffic; STiB0 - 31, STiC0 - 31, and STiD0 - 31 are not used. There are 32 output
groups with each group consisting of 4 streams (‘A’, ‘B’, ‘C’, and ‘D’). If the data rate is set to 16.384 Mbps or
8.192 Mbps, SToA0 - 31, SToB0 - 31, SToC0 - 31 and SToD0 - 31 are used for the output traffic. If the data rate is
set to 32.768 Mbps, SToA0 - 31 and SToB0 - 31 are used for the output traffic; STiC0 - 31 and STiD0 - 31 are in
high impedance. When the data rate is set to 65.536 Mbps, SToA0 - 31 are used for the output traffic; SToB0 - 31,
SToC0 - 31, and SToD0 - 31 are in high impedance.
By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which
can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other ST-BUS/GCI-Bus devices.
Overview
Functional Description
D18
C19
A20
B21
A22
E17
Pin
Name
TRST
PWR
TMS
TDo
TCK
TDi
IEEE 1149.1 Test Access Port (TAP)
Device Reset (5 V Tolerant Schmitt-Triggered Input)
Asynchronous reset input used to initialize the ZL50074.
0 = Reset
1 = Normal
See Section 9.0, Power-up and Initialization of the ZL50074 for
detailed description of Reset state.
Test Data (5 V Tolerant Input with Internal Pull-up)
Serial test data input. When not used, this input may be left
unconnected.
Test Data (3.3 V Output)
Serial test data output
Test Clock (5 V Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic
Test Reset (5 V Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
Test Mode Select (5 V Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
When not used, this pin is pulled high by an internal pull-up resistor
and may be left unconnected.
Zarlink Semiconductor Inc.
ZL50074
13
Description
Data Sheet