ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 45

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.8
The Global Rate Control Register is used to select the data rate of all the input and output streams. On power-up,
the GBR bits are both reset to 0, corresponding to a rate of 8.192 Mbps.
31 - 2
1 - 0
External Read/Write Address: 040290 - 040293
Reset Value: 0000
Bit
31
15
0
0
Global Rate Control Register
30
14
0
0
GBR1 - 0
Unused
Name
H
29
13
0
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Global Bit Rate Selection
Each input and output group can individually select different clock sources. If the internal
system clock is used as the clock source, all the above data rates are available. Other-
wise, the data rate cannot exceed the selected clock source’s rate.
28
12
0
0
27
11
GBR 1 - 0
0
0
00
01
10
11
26
10
0
0
H
Zarlink Semiconductor Inc.
25
9
0
0
ZL50074
24
0
8
0
45
Group B, C and D outputs are tristated
Group B, C and D inputs are unused
Group C and D outputs are tristated
Group C and D inputs are unused
16 Mbps - Group A, B, C and D
23
8 Mbps - Group A, B, C and D
0
7
0
Description
Input and Output Data Rate
32 Mbps - Group A and B
65 Mbps - Group A
22
6
0
0
21
5
0
0
20
4
0
0
19
3
0
0
18
0
2
0
Data Sheet
GBR
17
0
1
1
GBR
16
0
0
0