ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 23

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

8.3
In 16 bit mode (D16B = 1), D15 - 0 are used for data transfers to/from the ZL50074. D31 - 16 are unused and must
be connected to a defined logic level. D15 on the bus maps to Bit 31 and Bit 15 of the internal 32 bit memory or
register, D14 maps to Bit 30 and Bit 14, etc.
In 16 bit mode, the least significant address bit, A0, is not used, and must be connected to defined logic level. In this
case, address bit A1 and the Data Transfer Size inputs, SIZ1 - 0, identify which bytes are being accessed.
In Motorola Bus Mode (IM = 0), SIZ1 - 0 form active low data strobe signals, consistent with UDS and LDS available
on the MC68000 and MC68302 processors, as shown in Table 8.
In Intel Bus Mode (IM = 1), SIZ1 - 0 form active low byte enable signals, consistent with BE1 and BE0 available on
the Intel i960 processor, as shown in Table 8.
In both Intel and Motorola modes, the A1 address input is used to identify the word alignment in internal memory.
16-bit word alignment are shown in Table 9. An example of byte addressing is given in Table 10.
A1 = 0
A1 = 1
Pin Name
SIZ1
SIZ0
16 Bit Bus Operation
Microprocessor
16 Bit Data Bus
1. X - Don’t Care
D15 - 8
D15 - 0
Bits 31:16
Bits 15:0
D7 - 0
Equivalent Function
MC68000, MC68302
Motorola Mode
IM = 0
UDS
LDS
SIZ1
0
0
1
1
0
0
1
Table 9 - 16 Bit Mode Word Alignment
Table 8 - Byte Enable Signals
Zarlink Semiconductor Inc.
ZL50074
SIZ0
Intel Mode i960 Equivalent
1
1
0
0
0
0
1
23
Function
IM = 1
BE1
BE0
A1
X
0
1
0
1
0
1
1
Internal 32-Bit Memory
Data Bus Bytes Enabled
or Register
No access
Bits 31:24
Bits 23:16
Bits 31:16
Bits 15:8
Bits 15:0
Bits 7:0
D15-8
D7-0
Data Sheet