ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 28

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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The TAP signals are only applied when the ZL50074 is required to be in test mode. When in normal, non-test mode,
TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected.
10.2
The ZL50074 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG interface contains a
16-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during register scanning.
10.3
As specified in the IEEE 1149.1 standard, the ZL50074 JTAG Interface contains three test data registers:
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10.4
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDo. The data out of the
TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDo driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to V
driven from an external source. When JTAG is not in use, this pin must be tied low for normal operation.
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50074 core logic
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo
The Device Identification Register - The JTAG device ID for the ZL50074 is C39A14B
Instruction Register
Test Data Register
Boundary Scan Description Language (BSDL)
Version
Part Number
Manufacturer ID
LSB
<31:28>
<27:12>
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Zarlink Semiconductor Inc.
ZL50074
28
0000
1100 0011 1001 1010
0001 0100 101
1
DD_IO
H
when it is not
Data Sheet