ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet - Page 15

• Manufacturer Part Number: ZL50074GAC
• Description: 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Table 1 shows the maximum number of streams available at different bit rates. The ZL50074 deactivates unused
streams when operating at the higher bit rates as shown in Table 2.
All TDM input and output data streams operate at the same rate, programmed by the Global Rate Control Register
(Section 12.8).
2.0
The input timing for the ZL50074 can be set for one of four different frequencies. They can also be set for ST-BUS
or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the
device to be used. There are two additional input clocks and frame pulses that can be provided. CKi0 is used to
generate the internal clock. This clock is used for all the internal logic and can be used as one of the clocks that
defines the timing for the input and output data. The input stream clock source is selected by the ISSRC1 - 0 (bits 1
- 0) in the Group Control Register. The output stream clock source is selected by the OSSRC1 - 0 (bits 17 - 16) in
the Group Control Register.
The CKi0 and FPi0 input frequency is set via the CK_SEL1 - 0 pins as shown in Table 3. By default the CKi0 and
FPi0 pins accept ST-BUS, negative input timing. The input frame pulse format (ST-BUS/GCI-Bus), frame pulse
polarity, and clock polarity can be programmed by the GCISEL0 (bit 2), FPIPOL0 (bit 1), and CKIPSL0 (bit 0) in the
Input Clock Control Register (ICCR), as described in Section 12.4.
Two additional input clocks (CKi2 - 1) and frame pulses (FPi2 - 1) can be accepted. These signals can be
8.192 MHz, 16.384 MHz, 32.768 MHz or 65.536 MHz and the rates are automatically detected by the device.
These clocks and their frame boundaries must be phase aligned with the CKi0 and its frame boundary within a
30 ns skew but can have different jitter values. The clocks do not have to have the same frequency. If these
additional clocks are not used, the pins must be connected to a defined logic level.
These additional input clocks and frame pulses can be used as alternative clock sources for the input streams,
output streams, and output clocks / frame pulses. The input streams’ clock sources are controlled by the ISSRC1-0
(bits 1 - 0) in the Group Control Registers (GCR). The output streams’ clock sources are controlled by the
OSSRC1-0 (bits 17 - 16) in the Group Control Registers (GCR). The output clocks’ / frame pulses’ clock sources
are controlled by the CKO3SRC1-0 (bits 22-21), CKO2SRC1-0 (bits 15-14), CKO1SRC1-0 (bits 8-7), and
CKO0SRC1-0 (bits 1-0) in the Output Clock Control Register (OCCR). The clock sources can be set to either the
internal system clock or one of the three input clock signals. These are used to provide a direct interface to jittery
peripherals.
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
Input or Output Group n
STiCn / SToCn
STiDn / SToDn
STiAn / SToAn
STiBn / SToBn
(n = 0 - 31)
CK_SEL1
Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0
0
0
1
1
Table 2 - TDM Stream Bit Rates
Not Active
Not Active
Not Active
65 Mbps
Active
Zarlink Semiconductor Inc.
CK_SEL0
ZL50074
0
1
0
1
15
Not Active
Not Active
32 Mbps
Active
Active
Input CKi0 and FPi0
16.384 MHz
32.768 MHz
65.536 MHz
8.192 MHz
16 Mbps
Active
Active
Active
Active
8 Mbps
Active
Active
Active
Active
Data Sheet