BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 76

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

4.0 Registers
4.11 Receive/Transmit Status
TR_INVERT
4-24
0xE5—Receive Status 1 (RSTATUS_1)
—
7
TR_INVERT
bits is always in the LSB of the RSFIFO, as illustrated in
after every RD_RSIG interrupt, provided that the framer is not in an OUT_OF_SYNC state.
RSFIFO_I[1] is received first. Up to 48 bytes of receive signaling information can be read
from RSFIFO_O by the MC after it receives the RD_RSIG interrupt. The MC has 6 ms, 3 ms,
2 ms, or 1 ms (depending on the EXTRA_SIG_UPDATE configuration in the CMD_1 register
[0x3C0.3:4]) from the current RD_RSIG to the next RD_RSIG to read 48, 24, 16, or 8
RSFIFO_O entries. RSFIFO_I is loaded into RSFIFO_O at every RD_RSIG interrupt, before
RSFIFO_I is modified by the receiver.
the read pointer, and then reading up to 48 entries sequentially. RSFIFO_O[1] is read first.
Bt8954 increments the RSFIFO_O read pointer after read cycle. The pointer wraps around to
point to first entry (RSFIFO_O[1]) after the 48th entry (RSFIFO_O[48]) has been read.
Therefore, the RSFIFO_O read pointer needs to be reset only once (that is, during
initialization) if 48 entries are read every 6 ms.
RSFIFO_PTR_RST [0xC6] to reset the RSFIFO_I write pointer, and then writing up to 48
entries sequentially. RSFIFO_I[1] is written first.
address. The pointer wraps around to point to the first entry (RSFIFO_I[1]) after the 48th
entry (RSFIFO_I[48]) has been written.
copying RSFIFO_I into RSFIFO_O, provided the TEST_RSFIFO bit in RCMD_2 [0x91] is
set.
Tip/Ring Inversion—Indicates the receive framer acquired an inverted SYNC word A or B,
indicating the receive tip and ring wire pair connections are reversed. Bt8954 automatically
inverts the sign bits of all received data as it is presented on the RDAT input when inversion is
detected. TR_INVERT is updated each time the receive framer state transitions from
OUT_OF_SYNC to SYNC_ACQUIRED.
The number of signaling bits is set in TCM2_2 address [0x87]. The LSB of the signaling
Up to 48 bytes of receive signaling information are loaded into RSFIFO_I by the receiver
MC access to RSFIFO_O is provided by first writing to RSFIFO_PTR_RST [0xC6] to reset
For testing purposes, MC write access to RSFIFO_I is provided by first writing to
Bt8954 increments the RSFIFO_I write pointer after each write access to the RSFIFO’s
Also, for testing, writing any value to the UPDATE_RSFIFO_O register [0xDC] initiates
6
Figure 4-4. Example of Three Signaling Bits
RSFIFO_O_
UNDER
5
0 = SYNC_ACQUIRED with expected SYNC word
1 = SYNC_ACQUIRED with inverted SYNC word
RSFIFO_O_
MSB
1 2 3 X X X X X
OVER
4
Conexant
TSFIFO
RSFIFO_I_
UNDER
LSB
3
RSFIFO_I_OVER
Figure
2
MSB
X
X
4-4.
X
RSFIFO
X
RFIFO_UNDER
X
Voice Pair Gain Framer
1 2 3
1
LSB
RFIFO_OVER
N8954DSC
Bt8954
0