BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 53

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

For registers that contain less than 8 bits, assigned bits reside in LSB positions, unassigned bits are ignored
during write cycles, and are indeterminate during read cycles. The LSB in all registers is bit position 0.
All registers are randomly accessible. All register values written can be read back except where noted.
4.1 Register Types
The MC must read and write real-time registers (receive and transmit EOC, IND, S-bit, and status registers),
within a prescribed time interval (1–6 ms) after the DSL channel’s 6 ms frame interrupt to avoid reading or
writing transitory data values. Failure to read real-time registers within the prescribed interval results in a loss of
data.
changes modes, or responds to an error condition.
dictated by system architecture. Polled procedures can avoid reading transitory real-time data by monitoring the
Interrupt Status register bits [ISR; 0xD0] to determine when a particular group of registers has been updated.
Interrupt-driven and polled procedures must complete reading within the prescribed 1–6 ms interval following
DSL frame interrupts.
4.2 Register Groups
Bt8954 command, status, and real-time registers are divided into three groups:
Transmit registers reference data flow from the PCM channel to the DSL channel output. Receive registers
reference data flow from the DSL channel to the PCM channel outputs. Common registers affect overall
operation, primarily the PCM channel and the PLL.
N8954DSC
The MC writes to non-real-time command registers are event-driven and occur when the system initializes,
The MC reads can be interrupt-event driven, polled, or a combination of both, allowing the choice to be
The group of Transmit and Receive registers only affects operation or reports status of the DSL channel.
• Transmit
• Receive
• Common
4
4.0 Registers
Conexant
4-1