BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 46

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.0 Circuit Descriptions
3.9 PLL
Figure 3-23. Functional Diagram of the PLL
3-24
NOTE(S):
HCLK
Legend—
f
H
1/PLL_X
f
H = HCLK frequency;
FREF = f
3.9 PLL
The bit pump is the clock master of Bt8954, which in turn is a clock master of the
codecs. The PLL synthesizes a variety of (ADPCMCK, PCMCKO) frequency
pairs from HCLK (HCLK is 32 times the bit clock, BCLK).
the PLL architecture. First, HCLK is scaled by 1/PLL_X in the prescaler to
produce f
multiple (PLL_INT.FRACP) of f
give ADPCMCK, which in turn is scaled by 1/PLL_Y to give PCMCKO. The
frequency of GCLK, f
registers in the microcomputer interface.
[0xB5.6:5]. When PLL_P[1] = 1 and PLL_P[0] = 1, then the P_FACTOR is set to
8. When PLL_P[1] = 1 and PLL_P[0] = 0, then the P_FACTOR is set to 4. When
PLL_P[1] = 0, then the P_FACTOR is dependent on the value of PLL_W. This
allows you to adjust the value of GCLK. A lower value of GCLK lowers the
power requirements of the device and the maximum speed of the microprocessor
bus. The value for f
1/PLL_INT.FRACP
P_FACTOR is given by the PLL_P[1:0] bits of the PLL_SCALE register
H/PLL
_X
f
P = PCMCKO frequency;
REF
. The PLL output frequency, f
CORE
PLL
PLL
Conexant
GCLK
f
PLL
is either 196.608 MHz or 204.800 MHz.
=PLL_INT.FRACP x f
, is f
f
G = GCLK frequency;
1/P_FACTOR
PLL
REF
divided by P_FACTOR. GCLK clocks all the
. The f
PLL
PLL
REF
, is in general a non-integer
is post-scaled by 1/PLL_W to
f
A = ADPCMCK frequency.
1/PLL_W
1/PLL_Y
Voice Pair Gain Framer
Figure 3-23
OUT_OF_LOCK
ADPCMCK
PCMCKO
GCLK
N8954DSC
details
Bt8954