BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 70

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

4.0 Registers
4.9 Interrupt
4.9 Interrupt
The Interrupt registers are listed in
Table 4-7. Interrupt Registers
The Interrupt Status register (ISR) consists of independent read/write interrupt flags, one for each of eight
internal sources. Each flag bit is set and stays set when its corresponding source indicates that a valid interrupt
event occurred (for edge-triggered interrupts) or a valid interrupt condition exists (for level-sensitive interrupts).
If unmasked, this event causes the IRQ* output to be activated. Writing a logic 0 to an interrupt flag causes the
flag to be immediately cleared. Attempting to clear a flag whose underlying condition still exists does not
immediately clear the flag, but allows it to remain set until the underlying condition expires, at which time the
flag is cleared automatically. The clearing of an unmasked flag causes the IRQ* output to return to an inactive
state, if no other unmasked interrupt flags are set.
SIG_FIFO_ERR
RD_RSIG
LD_TSIG
4-18
0xD0—Interrupt Status Register (ISR)
SIG_FIFO_ERR
Address
0xD0
0xD1
7
Register Label
Signaling FIFO Error Interrupt—Informs the MC that a signaling FIFO error has occurred
(TSFIFO_I_OVER or TSFIFO_I_UNDER or TSIFIFO_O_OVER or TSFIFO_O_UNDER or
RSFIFO_I_OVER or RSFIFO_I_UNDER or RSFIFO_O_OVER or RSFIFO_O_UNDER).
Read Receive Signaling Interrupt—Instructs the MC to read new receive signaling
information before the next RD_RSIG interrupt occurs. This interrupt occurs every 6 ms,
3 ms, 2 ms, or 1 ms depending on the EXTRA_SIG_UPDATE configuration in the CMD_1
register [0xC0]. A RD_RSIG interrupt always occurs coincident with the start of the receive
DSL 6 ms frame, i.e., whenever an Rx interrupt occurs.
Load Transmit Signaling Interrupt—Instructs the MC to load new transmit signaling
information before the next LD_TSIG interrupt occurs. This interrupt occurs every 6 ms,
3 ms, 2 ms, or 1 ms depending on the EXTRA_SIG_UPDATE configuration in the CMD_1
register [0xC0]. A LD_TSIG interrupt always occurs coincident with the start of the transmit
DSL 6 ms frame, i.e., whenever a Tx interrupt occurs.
RD_RSIG
IMR
ISR
6
LD_TSIG
5
Table
Bits
0 = No interrupt
1 = SIG_FIFO_ERR interrupt
0 = No interrupt
1 = RD_RSIG interrupt
0 = No interrupt
1 = LD_TSIG interrupt
8
8
4-7.
PLL_ERR
4
Conexant
RX_ERR
3
Interrupt Status Register
Interrupt Mask Register
Name/Description
RX
2
TX_ERR
Voice Pair Gain Framer
1
N8954DSC
Bt8954
TX
0