BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 33

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Bt8954
Voice Pair Gain Framer
3.4.2 Transmit Signaling FIFOs
Figure 3-9. Double Buffering, Using Transmit S-Bits Registers
3.4.3 Payload Mux
N8954DSC
Blocks In DSL Frame
TSFIFO Output Regs
TSFIFO Input Regs
LD_TSIG
LD_TSIG
DSL_SUBFRAME_N (6 ms, 3 ms, 2 ms, 1 ms)
S
TSFIFO_O[1]
TSFIFO_I[1]
Block1
Payload
LD
Using two sets of transmit signaling FIFOs (TSFIFO_I and TSFIFO_O), double
buffering ensures that the MC has enough time to write new signaling
information without corrupting the signaling information being transmitted, as
illustrated in
In the default case, LD_TSIG is the same as the DSL 6 ms receive frame interrupt
that occurs upon the arrival of the 6 ms DSL frame. The LD_TSIG interrupt can
be made to occur more frequently than 6 ms by programming non-00 values in
the EXTRA_SIG_UPDATE bits in the CMD_1 register [0xC0]. Six, three, two,
or one millisecond(s) later, TSFIFO_I registers are loaded into TSFIFO_O
registers at the next LD_TSIG. TSFIFO_O, which is then transmitted, is not
thereby corrupted by the new TSFIFO_I values being written by the MC during
the next interval.
The Payload Mux multiplexes the overhead bits from the OH registers, payload
data from the PCM TFIFO, the SYNC word and the CRC bits that were calculated
for the previous transmit frame.
MC Loads TSFIFO_I REGS
The MC loads the TSFIFO_I registers after receiving the LD_TSIG interrupt.
S
TSFIFO_O[2]
TSFIFO_I[2]
Block2
Payload
LD
Figure
Conexant
3-9.
Computer
TSFIFO_I
DSL_SUBFRAME_N+1 (6 ms, 3 ms, 2 ms, 1 ms)
TSFIFO_O
Transmit TSFIFO_O REGS
3.0 Circuit Descriptions
TSFIFO_O[48]
S
TSFIFO_I[48]
3.4 Transmitter
Block48
Payload
LD
3-11