BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 58

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

4.0 Registers
4.4 Transmitter Registers
Transmit FIFO Water Level contains the number of BCLK cycles to delay from the PCM 6 ms frame to the start
of the DSL transmit SYNC word. A value of zero equals 1 BCLK delay.
4-6
0x85—Transmit FIFO Water Level (TFIFO_WL)
7
bits is always in the MSB of the TSFIFO. An example of three signaling bits is illustrated in
Figure
after it receives the Load Transmit Signaling Interrupt (LD_TSIG) from the transmitter. The
MC has 6 ms, 3 ms, 2 ms, or 1 ms, (depending on the EXTRA_SIG_UPDATE configuration in
the CMD_1 register [0xC0.4:3] from the current LD_TSIG to the next LD_TSIG to load 48,
24, 16, or 8 TSFIFO_I entries. TSFIFO_I is loaded into TSFIFO_O at every LD_TSIG
interrupt before TSFIFO_I is modified by the MC.
the write pointer, and then writing up to 48 entries sequentially. TSFIFO_I[1] is written first.
Bt8954 increments the TSFIFO_I write pointer after each write cycle to the TSFIFOs address.
The pointer wraps around to point to the first entry (TSFIFO_I[1]) after the 48th entry
(TSFIFO_I[48]) has been written. Therefore, the TSFIFO_I write pointer needs to be reset
only once (that is, during initialization) if 48 entries are written every 6 ms.
TSFIFO_PTR_RST [0xD5] to reset the TSFIFO_O read pointer, and then reading up to 48
entries sequentially. TSFIFO_O[1] is read first. Bt8954 increments the TSFIFO_O read
pointer after each read access to the TSFIFOs address. The pointer wraps around to point to
the first entry (TSFIFO_O[1]) after the 48th entry (TSFIFO_O[48]) has been read.
copying TSFIFO_I into TSFIFO_O, provided the TEST_TSFIFO bit in TCMD_1 [0x86] is
set.
The number of signaling bits is set in TCMD_2 address [0x87]. The MSB of the signaling
Up to 48 bytes of transmit signaling information can be loaded into TSFIFO_I by the MC
MC access to TSFIFO_I is provided by first writing to TSFIFO_PTR_RST [0xD5] to reset
For testing purposes, MC read access to TSFIFO_O is provided by first writing to
Also, for testing, writing any value to the UPDATE_TSFIFO_O address [0xDB] initiates
6
4-2.
Figure 4-2. Example of Three Signaling Bits
5
MSB
1 2 3 X X X X X
4
Conexant
TFIFO_WL[7:0]
TSFIFO
LSB
3
2
MSB
X
X
X
RSFIFO
X
X
Voice Pair Gain Framer
1 2 3
1
LSB
N8954DSC
Bt8954
0