BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 43

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Bt8954
Voice Pair Gain Framer
3.8.1 Microcomputer Read/Write
Figure 3-21. Functional Diagram of the Read and Write Controls
N8954DSC
3.8.1.1 Multiplexed
3.8.1.2 Separated
Address/Data Bus
Address/Data Bus
WR*/R/W*
RD*/DS*
MOTEL*
CS*
The MCI provides access to a 128-byte internal address space.
depicts the read/write controls. The MCI uses either an 8-bit-wide multiplexed
address-data bus (Intel style) or one 8-bit-wide data bus and another separate
7-bit-wide address bus (Motorola style) for external data communications. The
interface is configured with the inputs, MOTEL* and MUXED. MOTEL* low
selects Intel-type microcomputer and control signals: ALE, CS*, RD*, WR*.
MOTEL* high selects Motorola-type microcomputer and control signals: ALE,
CS*, DS*, R/W*. MUXED high configures the interface to use the multiplexed
address-data bus with both the address and data on the AD[7:0] pins. MUXED
low configures the interface to use separate address and data buses with the data
on the AD[7:0] pins and the address on the ADDR[6:0] pins.
The timing for a read or write cycle is stated in
Mechanical Specifications
places an address on the address-data bus which is then latched on the falling
edge of ALE. Data is placed on the address-data bus after CS* and RD* (or DS*)
go low. The read cycle is completed with the rising edge of CS* and RD* (or
DS*).
edge of ALE. The microcomputer places data on the address-data bus after CS*
and WR* (or DS*) go low. Motorola MCI has R/W* falling edge preceding the
falling edge of CS* and DS*. The rising edge of R/W* occurs after the rising
edge of CS* and DS*. Data is latched on the address-data bus on the rising edge
of WR* or DS*.
The timing for a read or write cycle using the separated address and data buses is
essentially the same as over the multiplexed bus. The one exception is that the
address must be driven onto the ADDR[6:0] bus rather than the AD[7:0] bus.
A write operation latches the address from the address-data bus at the falling
MUXED
Conexant
. During a read operation, an external microcomputer
ADDR[7:0]
AD[7:0]
ALE
Chapter 5.0, Electrical and
3.8 Microcomputer Interface
To Registers
From Registers
Read Strobe
Write Strobe
3.0 Circuit Descriptions
Figure 3-21
Address
3-21