BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 71

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Bt8954
Voice Pair Gain Framer
PLL_ERR
RX_ERR
RX
TX_ERR
TX
The Interrupt Mask register (IMR) consists of independent read/write mask bits for each ISR [0xD0] interrupt
flag. A logic 1 represents the masked condition, a logic 0 the unmasked condition. All mask bits behave
identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corresponding
interrupt flag from affecting the IRQ* output. Clearing a mask allows the interrupt flag to affect IRQ* output.
Unmasking an active interrupt flag immediately causes the IRQ* output to go active, if currently inactive.
Masking an active interrupt flag causes IRQ* to go inactive, if no other unmasked interrupt flags are set. Upon
RST* assertion, all IMR bits are automatically set to 1 to disable the IRQ* output.
SIG_FIFO_ERR
RD_RSIG
LD_TSIG
PLL_ERR
RX_ERR
RX
TX_ERR
TX
N8954DSC
0xD1—Interrupt Mask Register (IMR)
SIG_FIFO_ERR
7
PLL Error Interrupt—Indicates if PLL is in an out-of-lock state.
Receive Error Interrupt—Framer state transition to OUT_OF SYNC, RFIFO errors; CRC and
FEBE counter overflows are logically ORed to form RX_ERR.
Receive DSL 6 ms Frame Interrupt—Reported coincident with the start of the receive DSL
6 ms frame. This allows the MC to synchronize read access of the receive status registers.
Transmit Error Interrupt—Generated whenever the Transmit HDSL frame is repositioned or a
TFIFO underflow/overflow error occurs.
Transmit DSL 6 ms Frame Interrupt—Reported coincident with the start of the transmit DSL
6 ms frame. This allows the MC to synchronize read access of the transmit status
[TSTATUS_1; 0xE7] and write access to the real-time transmit DSL registers.
Mask the SIG_FIFO_ERR interrupt.
Mask the RD_RSIG interrupt.
Mask the LD_TSIG interrupt.
Mask the PLL error interrupt.
Mask the DSL receive error interrupt.
Mask the DSL 6 ms receive frame interrupt.
Mask the DSL transmit error interrupt.
Mask the DSL 6 ms transmit frame interrupt.
RD_RSIG
6
LD_TSIG
5
0 = PLL in-lock
1 = PLL out-of-lock
0 = No interrupt
1 = Receive error interrupt
0 = No interrupt
1 = Receive frame interrupt
0 = No interrupt
1 = Transmit error interrupt/Transmit HDSL Frame Repositioned
0 = No interrupt
1 = Transmit frame interrupt
PLL_ERR
4
Conexant
RX_ERR
3
RX
2
TX_ERR
1
4.0 Registers
4.9 Interrupt
TX
0
4-19