BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 25

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Bt8954
Voice Pair Gain Framer
3.2.2 Differences Between the DSL and HDSL T1/E1 Frame Formats
3.2.3 Overhead Bit Allocation
N8954DSC
3.2.2.1 EXTRA_Z_BIT
Option
The DSL frame format is similar to the T1/E1 frame formats that are transported
on one HDSL loop. The main difference is due to the number of S-bits. While
fixed as 1 F-bit/block and 1 Z-bit/block for the T1 and E1 HDSL frame formats, it
can vary between 0 and 8 bits for the DSL frame format. The number of S-bits is
allowed to vary up to 8 bits so that a variable number of D-channel bit rates (up to
64 kbps) can be supported.
Some systems (e.g., PCM11) require an extra 8 kbps Z-bit field in addition to the
basic frame structure outlined in
block of the DSL frame has an extra Z-bit (preceding the S-bits field) that can be
enabled for transmit when EXTRA_Z_BIT in Command register 1
[CMD_1; 0xC0.5] is set. For example, a PCM11 system can have a 784 kbps bit
rate consisting of 704 kbps (11x64 kbps) of payload, 8 kbps of overhead, 64 kbps
of signaling information, and 8 kbps of the extra Z-bit. This extra Z-bit field is a
dummy field and is not accessible through the MC.
The overhead bit allocation of the DSL frame is the same as that of the HDSL
frame given in
Table 3-1. DSL Frame Structure and Overhead Bit Allocation (1 of 2)
DOH Bit
Number
17–20
21–22
27–30
31–32
1–14
15
16
23
24
25
26
33
34
35
36
Table
SW1–SW14
eoc1–eoc4
eoc6–eoc9
crc1–crc2
crc3–crc4
Symbol
eoc5
losd
febe
rrbe
rcbe
rega
ps1
ps2
bpv
hrp
Conexant
3-1.
SYNC Word
Loss of Signal
Far End Block Error
Embedded Operations Channel
Cyclic Redundancy Check
HTU-R Power Status
Power Status Bit 2
Bipolar Violation
Embedded Operations Channel
Embedded Operations Channel
Cyclic Redundancy Check
HDSL Repeater Present
Repeater Remote Block Error
Repeater Central Block Error
Repeater Alarm
Payload Blocks 13–24
Payload Blocks 1–12
Figure
3-2. To accommodate such systems, each
Bit Name
3.0 Circuit Descriptions
3.2 DSL Frame Format
DOH Register Bit
EOC[12]–EOC[9]
EOC[7]–EOC[4]
IND[12]
IND[11]
IND[10]
EOC[8]
IND[9]
IND[8]
IND[7]
IND[6]
IND[5]
IND[4]
—
—
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3-3