BT8954 CONEXANT [Conexant Systems, Inc], BT8954 Datasheet - Page 19

• Manufacturer Part Number: BT8954
• Description: VOICE PAIR GAIN FRAMER
• Manufacturer: CONEXANT [Conexant Systems, Inc]

Bt8954
Voice Pair Gain Framer
Table 2-1. Hardware Signal Definitions (1 of 4)
N8954DSC
MOTEL*
ALE
CS*
RD*/DS*
WR*/R/W*
AD[7:0]
ADDR[6:0]
MUXED
IRQ*
RST*
Pin Label
Number
19–24,
28–35
Pin
36
15
12
13
14
16
37
25
38
Motorola/Intel*
Address Latch Enable
Chip Select
Read/Data Strobe
Write/Read/Write
Address-Data[7:0]
Address Bus [6:0]
(Not Multiplexed)
Addressing Mode Select
Interrupt Request
Reset
Signal Name
Conexant
I/O
I/O
OD
O,
I
I
I
I
I
I
I
I
Selects between Motorola and Intel handshake conventions
for the RD*/DS* and WR*/R/W* signals.
Falling-edge-sensitive input. The value of AD[7:0] when
MUXED = 1, or of ADDR[7:0] when MUXED = 0, is internally
latched on the falling edge of ALE.
Active-low input used to enable read/write operations on the
Microcomputer Interface (MCI).
Bimodal input for controlling read/write access on the MCI.
active-low data strobe, DS*. Internal data is output on
AD[7:0] when DS* = 0 and R/W* = 1. External data is
internally latched from AD[7:0] on the rising edge of DS*
when R/W* = 0.
active-low read strobe RD*. Internal data is output on
AD[7:0] when RD* = 0. Write operations are not controlled
by RD* in this mode.
Bimodal input for controlling read/write access on the MCI.
read/write select line, R/W*. Internal data is output on
AD[7:0] when DS* = 0 and R/W* = 1. External data is
internally latched from AD[7:0] on the rising edge of DS*
when R/W* = 0.
an active-low write strobe, WR*. External data is internally
latched from AD[7:0] on the rising edge of WR*. Read
operations are not controlled by WR* in this mode.
Eight-bit bidirectional multiplexed address-data bus.
AD[7] = MSB, AD[0] = LSB. Usage is controlled using the
MUXED signal.
Provides a glueless interface to microcomputers with
separate address and data buses. ADDR[6] = MSB, ADDR[0]
= LSB. Usage is controlled using the MUXED signal.
Controls the MCI addressing mode.
signal for address and data (typical of Intel processors).
address input and AD[7:0] for data only (typical of Motorola
processors).
Active-low open-drain output that indicate requests for
interrupt. Asserted whenever at least one unmasked interrupt
flag is set. Remains inactive whenever no unmasked
interrupt flags are present.
Asynchronous, active-low, level-sensitive input that resets
the framer.
MOTEL* = 1 for Motorola protocol: DS*, R/W*;
MOTEL* = 0 for Intel protocol: RD*, WR*.
When MOTEL* = 1 and CS* = 0, RD*/DS* behaves as an
When MOTEL* = 0 and CS* = 0, RD*/DS* behaves as an
When MOTEL* = 1 and CS* = 0, WR*/R/W* behaves as a
When MOTEL* = 0 and CS* = 0, WR*/R/W* behaves as
When MUXED = 1, the MCI uses AD[7:0] as a multiplexed
When MUXED = 0, the MCI uses ADDR[7:0] as the
Definition
2.0 Pin Descriptions
2-3