ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 9

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin #
56
57
58
59
60
61
62
63
64
REF2_SYNC REF2 Synchronization Frame Pulse (Input). This is the 2 kHz or 8 kHz (multi) frame
SEC_MSTR
FASTLOCK
APP_SEL0
TIE_CLR
Name
REF1
REF2
V
IC
DD
Reference (Input). See REF0 pin description.
Reference (Input). See REF0 pin description.
pulse synchronization input associated with the REF2 reference. While the PLL is locked
to the REF2 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
Secondary Master Mode Selection (Input). A logic low at this pin selects the Primary
Master mode of operation with 1.8 Hz or 3.6 Hz DPLL loop filter bandwidth. A logic high
selects Secondary Master mode which forces the PLL to clear its TIE corrector circuit and
lock to the selected reference using a high bandwidth loop filter and a phase slope
limiting of 9.5 ms/s.
Application Selection (Input). See APP_SEL1 pin description.
Positive Supply Voltage. +3.3 V
Internal Connection. Connect to GND.
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
Fast Lock (Input). Set temporarily high to allow the ZL30105 to quickly lock to the input
reference (one second locking time).
Zarlink Semiconductor Inc.
ZL30105
9
DC
nominal
Description
Data Sheet