ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 10

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.0
The ZL30105 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization
signals to interface circuits for the following types of primary rate digital transmission links, see Table 1:
Figure 1 is a functional block diagram of the ZL30105 which is described in the following sections.
2.1
The ZL30105 accepts three simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected
as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs.
The use of the combined REF2 and REF2_SYNC inputs allows for a very accurate phase alignment of the output
frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF2_SYNC input. This feature supports the
implementation of Primary and Secondary Master system clocks in AdvancedTCA or H.110 systems.
2.2
The input references are monitored by three independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
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DS1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E
E1 compliant with ITU-T G.703 and ETSI ETS 300 011
PDH compliant with Telcordia GR-1244-CORE Stratum 3
SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE
Reference Select Multiplexer (MUX)
Reference Monitor
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this
information to the various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock
is within the selected accuracy range, see Table 1.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
Functional Description
Zarlink Semiconductor Inc.
ZL30105
10
Data Sheet