ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 34

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ZL30105QDG

Manufacturer Part Number
ZL30105QDG
Description
T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet

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5.5
Carrier-Class Telecommunications Equipment deployed in today’s networks guarantee better than 99.999%
operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted
service is achieved by fully redundant architectures with hot swappable cards like an ECTF H.110 or a PICMG
AdvancedTCA™ compliant system. Timing for these types of systems can be generated by the ZL30105 which
supports primary/secondary master timing protection switching.
The architecture shown in Figure 24 and Figure 25 is based on the ZL30105 being deployed on two separate timing
cards; the primary master timing card and the secondary master timing card. In normal operation the primary
master timing card receives synchronization from the network and provides timing for the whole system. The
redundant secondary master timing card is phase locked to the backplane clock and frame pulse through its REF2
and REF2_SYNC inputs. These two designated inputs allow the secondary master timing card to track the primary
master timing card clocks with minimal phase skew. When the primary master timing card fails unexpectedly (this
failure is not related to reference failure) then all switch cards or line cards will detect this failure and they will switch
to the timing supplied by the secondary master timing card. The secondary master timing card will be promoted to
primary master and switch from using the REF2 and REF2_SYNC inputs to one of the REF0 or REF1 inputs.
Clock Redundancy System Architecture
Primary Master Timing Card
Secondary Master Timing Card
Figure 24 - Typical Clocking Architecture of an ECTF H.110 System
REF0
REF1
REF2
REF2_SYNC
REF0
REF1
REF2
REF2_SYNC
ZL30105
ZL30105
SEC_MSTR
SEC_MSTR
Master/Slave
Master/Slave
Control
Control
F8o
F8o
C8o
C8o
0
1
CT_NETREF_2
CT_NETREF_1
CT_FRAME_A
CT_C8_A
Zarlink Semiconductor Inc.
ZL30105
Backplane
34
CT_FRAME_B
CT_C8_B
MT90866
H.110 DX
MT90866
H.110 DX
Data Sheet

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