ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 13

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC input signal is also
monitored for failure (see Figure 8).
Sync Ratio Monitor (SRM): This monitor detects if the REF2_SYNC signal is a 2 kHz or an 8 kHz signal. It also
checks the number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the
integrity of the REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2
reference clock in a single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2
and REF2_SYNC inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL
will abandon the mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2
reference will be used for synchronization.
2.3
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
C20: 20 MHz master oscillator clock
Time Interval Error (TIE) Corrector Circuit
C20 Clock Accuracy
+4.6 ppm
-4.6 ppm
Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11
0 ppm
-16.6
REF2
frequency
REF2
REF2_SYNC
-15
-13.8
Figure 8 - REF2_SYNC Reference Monitor
-12
-10
-9.2
-7.4
Zarlink Semiconductor Inc.
-4.6
C20
-4.6
-5
ZL30105
C20
Reference
0
0
Monitor
Circuit
SYNC
13
C20
4.6
4.6
5
7.4
9.2
10
12
13.8
15
to DPLL
16.6
Frequency offset [ppm]
Out of Range
In Range
Out of Range
In Range
Out of Range
In Range
Data Sheet