ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 39

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ZL30105QDG

Manufacturer Part Number
ZL30105QDG
Description
T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet

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AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when
TIE_CLR = 0 (see Figure 27).
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
10
12
13
11
1
2
3
4
5
6
7
8
9
2 kHz reference input to F2ko delay
2 kHz reference input to F8/F32o delay
8 kHz reference input to F8/F32o delay
1.544 MHz reference input to C1.5o delay
1.544 MHz reference input to F8/F32o delay
2.048 MHz reference input to C2o delay
2.048 MHz reference input to F8/F32o delay
8.192 MHz reference input to C8o delay
8.192 MHz reference input to F8/F32o delay
16.384 MHz reference input to C16o delay
16.384 MHz reference input to F8/F32o delay
19.44 MHz reference input to C19o delay
19.44 MHz reference input to F8/F32o delay
Characteristics
Zarlink Semiconductor Inc.
ZL30105
39
t
t
t
t
REF1.5_F8D
t
t
REF2k_F8D
REF16_F8D
REF19_F8D
REF2_F8D
REF8_F8D
Symbol
t
t
t
t
t
REF1.5D
t
t
REF2kD
REF8kD
REF16D
REF19D
REF2D
REF8D
-27.2
Min.
29.4
-2.0
-0.9
-0.5
-1.1
-0.2
-1.5
-0.1
-1.1
-1.7
0.3
0.4
-26.5
Max.
30.3
-0.3
-0.2
-0.2
-0.5
-1.1
1.0
0.5
0.6
1.2
1.9
1.0
Data Sheet
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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