ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 14

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 27. The speed of the phase alignment correction is limited by the selected loop filter bandwidth and the
phase slope limit (see Table 2). Convergence is always in the direction of least phase travel. TIE_CLR can be kept
low continuously; in that case the output clocks will always align with the selected input reference. This is illustrated
in Figure 9.
The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal
mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value
thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode.
(see Figure 10). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE
circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode.
This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the
input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30105 is
always hitless unless TIE_CLR is kept low continuously.
REF1
REF1
REF0
REF0
Output
Clock
Output
Clock
locked to REF1
locked to REF0
TIE_CLR = 0
Figure 9 - Timing Diagram of Hitless Reference Switching
Zarlink Semiconductor Inc.
ZL30105
14
REF0
REF1
REF0
REF1
Output
Clock
Output
Clock
locked to REF1
locked to REF0
TIE_CLR = 1
Data Sheet