ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 33

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ZL30105QDG

Manufacturer Part Number
ZL30105QDG
Description
T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet

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5.3
The ZL30105 requires that the 3.3 V is not powered after the 1.8 V. This is to prevent the risk of latch-up due to the
presence of parasitic diodes in the IO pads.
Two options are given:
1. Power-up 3.3 V first, 1.8 V later
2. Power up 3.3 V and 1.8 V simultaneously ensuring that the 3.3 V power is never lower than 1.8 V minus a few
5.4
A simple power up reset circuit with about a 300 µs reset low time is shown in Figure 23. Resistor R
protection only and limits current into the RST pin during power down conditions. The reset low time is not critical
but should be greater than 300 ns.
hundred millivolts (e.g., by using a schottky diode or controlled slew rate)
Power Up Sequence
Reset Circuit
ZL30105
ZL30105
The 100 Ω resistor and the 1 µH inductor may improve
stability and are optional.
Figure 22 - Crystal Oscillator Circuit
Figure 23 - Power-Up Reset Circuit
OSCi
OSCo
1 MΩ
RST
Zarlink Semiconductor Inc.
ZL30105
100 Ω
1 kΩ
R
33
P
20 MHz
10 kΩ
R
+3.3 V
1 µH
10 nF
C
Data Sheet
P
is for

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