ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 11

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer re-qualify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure
4 where REF0 experiences disruptions while REF1 is stable.
REF0
dis/requalify
timer on REF0
REF_OOR0
(internal signal)
REF_FAIL0
HOLDOVER
REF_SEL
REF0 /
REF1 /
REF2
Reference Frequency
Precise Frequency
Coarse Frequency
REF0
SCM or CFM failure
Single Cycle
Detector
2.5 s
Monitor
Monitor
Monitor
REF1
Figure 4 - Behaviour of the Dis/Re-qualify Timer
Figure 3 - Reference Monitor Circuit
10 s
OR
Zarlink Semiconductor Inc.
ZL30105
REF_OOR = reference out of range.
REF_DIS= reference disrupted.
Both are internal signals.
dis/requalify
11
timer
REF0
SCM or CFM failure
OR
OR
REF_OOR
REF_DIS
Reference
select
state machine
Mode select
state machine
REF1
Data Sheet
REF_SEL1:0
HOLDOVER
REF_FAIL0 /
REF_FAIL1 /
REF_FAIL2