ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet
ZL30105QDG
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ZL30105QDG Summary of contents
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... HOLDOVER Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA™ and H.110 ZL30105QDG • Less than 0.6 ns clocks and frame pulses • Manual or Automatic hitless reference switching • ...
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Description The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks. The ZL30105 generates SBI, ST-BUS and other TDM ...
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Pin Description ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ZL30105 F4/F65o F16o 50 AGND IC 52 REF_SEL0 REF_SEL1 54 REF0 REF1 56 ZL30105 REF2 REF2_SYNC 58 SEC_MSTR APP_SEL0 TIE_CLR FASTLOCK Figure 2 - Pin Connections (64 ...
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Pin Description Pin # Name 1 GND Ground Positive Supply Voltage. +1.8 V CORE 3 LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected ...
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Pin # Name 19 RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the ...
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Pin # Name 42 C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency is selected via the OUT_SEL2 pin, see ...
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Pin # Name 56 REF1 Reference (Input). See REF0 pin description. 57 REF2 Reference (Input). See REF0 pin description. 58 REF2_SYNC REF2 Synchronization Frame Pulse (Input). This is the 2 kHz or 8 kHz (multi) frame pulse synchronization input associated ...
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Functional Description The ZL30105 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization signals to interface circuits for the following types of primary rate digital transmission links, see Table 1: • DS1 compliant with ANSI T1.403 ...
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Reference Frequency Detector REF0 / Precise Frequency REF1 / Monitor REF2 Coarse Frequency Monitor Single Cycle Monitor Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure ...
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When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the REF_FAIL status pin at ...
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C20 Clock Accuracy 0 ppm +4.6 ppm -4.6 ppm -16.6 -13.8 -15 C20: 20 MHz master oscillator clock Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11 In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC ...
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The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This results in a phase alignment between the input reference signal and the output clocks and frame pulses as ...
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HMS = 0 Normal mode REF Output Clock Phase drift in Holdover mode REF Output Clock Return to Normal mode REF Output Clock TIE_CLR=0 REF Output Clock Figure 10 - Timing Diagram of Hitless Mode Switching Examples: HMS=1: When ten ...
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Holdover mode - the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode - the maximum phase discontinuity in the ...
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Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of ...
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Control and Modes of Operation 3.1 Application Selection APP_SEL Application 00 DS1 PDH Stratum 3 11 SDH Table 1 - Application Selection and the Out of Range Limits 3.2 Loop Filter and Limiter Selection The loop ...
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Output Clock and Frame Pulse Selection The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). These ...
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Holdover Mode Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted. In Holdover Mode, the ZL30105 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on ...
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REF_DIS=0 and REF_CH=0 and HMS=0 RST (HOLDOVER=1) REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal. REF_CH= 1: Reference change, a transition in the reference selection (see Figure 14 change in the REF_SEL pins. ...
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REF_SEL LOCK Note: LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 13 - Reference Switching in Normal Mode 3.5.2 Automatic Reference Switching In the automatic mode of operation (MODE_SEL1:0 = 11), the ZL30105 automatically selects a ...
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The mode selection state machine behaves differently in Automatic mode in that when both reference REF0 and reference REF1 are out of range (REF_OOR=1), the state machine will select the Holdover state. In Normal mode the reference out of range ...
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SCM or CFM failure REF0 REF_DIS0 (internal signal) REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 LOCK 1 s Note: this scenario is based on REF1 remaining good throughout the duration. Figure 16 - Automatic Reference Switching - Coarse Reference Failure ...
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Frequency Precision failure REF0 REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL LOCK Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 17 ...
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The method of synchronization using REF2 and REF2_SYNC is enabled as soon as a valid 2 kHz or 8 kHz frame pulse is detected on the REF2_SYNC input. The REF2_SYNC pulse must be generated from the clock that is present ...
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Active Timing Card MODE_SEL1:0=11 REF_SEL1:0=10 SEC_MSTR=0 BITS 0 clock BITS 1 clock BITS 0 clock BITS 1 clock MODE_SEL1:0=11 REF_SEL1:0=10 SEC_MSTR=0 Redundant Timing Card Figure 19 - Clock Redundancy with Two Independent Timing Cards The following is an example of ...
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When the redundant timing card is switched to becoming the active timing card, the system controller should do the following: • select Primary Master mode, SEC_MSTR=0 • select Automatic mode, MODE_SEL1:0=11 The new active timing card will automatically select a ...
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Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 4.1 Jitter Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as ...
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Range Pull-in Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into synchronization. 4.8 Lock Range This is the input frequency range over which the synchronizer must ...
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Applications This section contains ZL30105 application specific details for power supply decoupling, reset operation, clock and crystal operation. 5.1 Power Supply Decoupling It is recommended to place a 100 nF decoupling capacitor close to each pair of power and ...
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Clock Oscillator When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. 1 Frequency 2 Tolerance 3 Rise & ...
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ZL30105 5.3 Power Up Sequence The ZL30105 requires that the 3 not powered after the 1.8 V. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options ...
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Clock Redundancy System Architecture Carrier-Class Telecommunications Equipment deployed in today’s networks guarantee better than 99.999% operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted service is achieved by fully redundant architectures ...
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CLK3A CLK3B ZL30105 REF0 REF1 C19o REF2 F8o REF2_SYNC SEC_MSTR 0 Master/Slave Control Primary Master Timing Card ZL30105 REF0 REF1 C19o REF2 F8o REF2_SYNC SEC_MSTR 1 Master/Slave Control Secondary Master Timing Card Figure 25 - Typical Clocking Architecture of a ...
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Characteristics 6.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply voltage 2 Core supply voltage 3 Voltage on any digital pin 4 Voltage on OSCi and OSCo pin 5 Current on any pin 6 Storage temperature ...
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AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 26). Characteristics 1 Threshold Voltage 2 Rise and Fall Threshold Voltage High 3 Rise and Fall Threshold Voltage Low * Supply voltage and operating temperature are as per Recommended ...
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REF0/1/2 output clock with the same frequency as REF F8_32o Figure 27 - REF0/1/2 Input Timing and Input to Output Timing AC Electrical Characteristics* - Input timing for REF2_SYNC (see Figure 28). REF2_SYNC Characteristics frequency 1 REF2_SYNC lead time 2 ...
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AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 27). Characteristics 1 2 kHz reference input to F2ko delay 2 2 kHz reference input to F8/F32o delay 3 8 ...
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AC Electrical Characteristics output timing (see Figure 29). Characteristics 1 C2o delay 2 C2o pulse width low 3 F4o pulse width low 4 F4o delay 5 C4o pulse width low 6 C4o delay 7 F8o pulse width high ...
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F8o C2o F4o C4o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure Output Timing Referenced to F8/F32o ZL30105 t ...
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AC Electrical Characteristics* - DS1 output timing (see Figure 30). Characteristics 1 C1.5o delay 2 C1.5o pulse width low 3 C3o delay 4 C3o pulse width low 5 Output clock and frame pulse rise time 6 Output clock and frame ...
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AC Electrical Characteristics* - DS2, E2, E3 and DS3 Output Timing (see Figure 32). Characteristics 1 C6o delay 2 C6o pulse width low 3 C8.4o delay 4 C8.4o pulse width low 5 C34o delay 6 C34o pulse width low 7 ...
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AC Electrical Characteristics* - OSCi 20MHz Master Clock Input Characteristics 1 Oscillator Tolerance - DS1 2 Oscillator Tolerance - E1 3 Oscillator Tolerance - PDH Stratum 3 4 Oscillator Tolerance - SDH 5 Duty cycle 6 Rise time 7 Fall ...
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Performance Characteristics* - Functional (continued) Characteristics 10 E1 (1.8 Hz filter - all reference frequencies) 11 PDH Stratum 3 (1.8 Hz filter - all reference frequencies) 12 SDH (3.6 Hz filter - all reference frequencies) 13 SEC_MSTR = 1 (14 ...
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Performance Characteristics*: Input Wander and Jitter Tolerance Conformance Input reference frequency 1 1.544 MHz 2 2.048 MHz 3 19.44 MHz * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Output Jitter Generation - ANSI T1.403 ...
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Performance Characteristics*: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Measurement Signal Filter OC-3 Interface 1 C19o 65 kHz to 1.3 MHz 2 12 kHz to1.3 MHz (Category II ...
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Performance Characteristics* - Unfiltered Jitter Generation Characteristics 1 C1.5o (1.544 MHz) 2 C2o (2.048 MHz) 3 C3o (3.088 MHz) 4 C4o (4.096 MHz) 5 C6o (6.312 MHz) 6 C8o (8.192 MHz) 7 C8.4o (8.448 MHz) 8 C16o (16.384 MHz) 9 ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...