ZL30105QDG ZARLINK [Zarlink Semiconductor Inc], ZL30105QDG Datasheet - Page 7

• Manufacturer Part Number: ZL30105QDG
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
C6/8.4/34/44o Clock 6.312 MHz, 8.448 MHz, 34.368 MHz or 44.736 MHz (Output). This output is used
OUT_SEL2
OUT_SEL1
OUT_SEL0
APP_SEL1
AV
AGND
AGND
AGND
AGND
Name
OSCo
C1.5o
OSCi
AV
AV
AV
C19o
GND
F2ko
RST
V
C3o
IC
CORE
DD
DD
DD
DD
Reset (Input). A logic low at this input resets the device. On power up, the RST pin must
be held low for a minimum of 300 ns after the power supply pins have reached the
minimum supply voltage. When the RST pin goes high, the device will transition into a
Reset state for 3 ms. In the Reset state all outputs will be forced into high impedance.
Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
Internal Connection. Leave unconnected.
Ground. 0 V
Application Selection 1 (Input). This input combined with APP_SEL0 selects the
application that the ZL30105 is optimized for, see Table 1 on page 18.
Positive Supply Voltage. +3.3 V
Output Selection 2 (Input). This input selects the signals on the combined output clock
and frame pulse pins, see Table 3 on page 19.
Output Selection 1 (Input). This input combined with OUT_SEL0 selects the signals on
the combined output clock pin C6/8.4/34/44o, see Table 3 on page 19.
Output Selection 0 (Input). See OUT_SEL1 description.
Positive Analog Supply Voltage. +3.3 V
in DS2, E2, E3 or DS3 applications. The output frequency is selected via the OUT_SEL1
and OUT_SEL0 pins, see Table 3 on page 19.
Clock 3.088 MHz (Output). This output is used in DS1 applications.
Clock 1.544 MHz (Output). This output is used in DS1 applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Analog Ground. 0 V
Analog Ground. 0 V
Positive Analog Supply Voltage. +1.8 V
Positive Analog Supply Voltage. +3.3 V
Positive Analog Supply Voltage. +3.3 V
Multi Frame Pulse (Output). This is a 2 kHz 51 ns active high framing pulse, which
marks the beginning of a multi frame.
Clock 19.44 MHz (Output). This output is used in SDH applications.
Analog Ground. 0 V
Analog Ground. 0 V
Zarlink Semiconductor Inc.
ZL30105
7
DC
nominal
Description
DC
DC
DC
DC
nominal
nominal
nominal
nominal
Data Sheet