AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 803

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

35.2.9
35.2.10
35.2.11
35.2.12
32099D–06/2010
TWI
PWMA
CAT
aWire
5. SPI mode fault detection enable causes incorrect behavior
1. TWIM.SR.IDLE goes high immediately when NAK is received
1. BUSY bit is never cleared after writes to the Control Register (CR)
2. Incoming peripheral events are discarded during duty cycle register update
1. CAT asynchronous wake will be delayed by one AST peripheral event period
1. aWire CPU clock speed robustness
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
The aWire memory speed request command counter wraps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
AT32UC3L016/32/64
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