AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 202

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.14
32099D–06/2010
Interrupts
The SCIF has 14 interrupt sources:
The interrupt sources will generate an interrupt request if the corresponding bit in the Interrupt
Mask Register is set. The interrupt sources are ORed together to form one interrupt request. The
SCIF will generate an interrupt request if at least one of the bits in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from
the SCIF will remain active until all the bits in ISR are cleared.
• AE - Access Error:
• BRIFARDY - Backup Register Interface Ready.
• DFLL0RCS - DFLL Reference Clock Stopped:
• DFLL0RDY - DFLL Ready:
• DFLL0LOCKLOSTA - DFLL lock lost on Accurate value:
• DFLL0LOCKLOSTF - DFLL lock lost on Fine value:
• DFLL0LOCKLOSTC - DFLL lock lost on Coarse value:
• DFLL0LOCKA - DFLL Locked on Accurate value:
• DFLL0LOCKF - DFLL Locked on Fine value:
• DFLL0LOCKC - DFLL Locked on Coarse value:
• BODDET - Brown out detection:
• SM33DET - Supply Monitor 3.3V Detector:
• VREGOK - Voltage Regulator OK:
• OSCRDY - OSCReady:
• OSC32RDY - 32KHz Oscillator Ready:
– Set when a protected SCIF register was accessed without first being correctly
– Set on 0 to 1 transition on the PCLKSR.BRIFARDY bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTA bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTF bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTC bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLLOCKA bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLLOCKF bit is detected.
– Set on 0 to 1 transition on the PCLKSR.DFLLLOCKC bit is detected.
– Set on 0 to 1 transition on the PCLKSR.BODDET bit is detected.
– Set on 0 to 1 transition on the PCLKSR.SM33DET bit is detected.
– Set on 0 to 1 transition on the PCLKSR.VREGOK bit is detected.
– Set on 0 to 1 transition on the PCLKSR.OSCRDY bit is detected.
– Set on 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected.
unlocked.
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