AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 197

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.3.7
14.5.3.8
14.5.3.9
14.5.4
32099D–06/2010
Generic clocks
Start-up
Accuracy
Internal synchronization
The amplitude of the frequency variation can be selected by setting the AMPLITUDE field in
DFLL0SSG register. If the AMPLITUDE is set to zero the SSG will toggle on the LSB of the FINE
value, setting AMPLITUDE to one the SSG will add the sequence {1,-1, 0} to the FINE value on
every source clock cycle.
The step size of the SSG is set in the STEPSIZE bit field in the DFLL0SSG register. Setting the
STEPSIZE to zero or one will result in a step size equal to one. If the step size is set to n the out-
put value from the SSG will be incremented/decremented by n on every tick of the source clock.
Figure 14-5. Spread Spectrum Generator Block Diagram.
The Spread Spectrum Generator can operate both in open and closed loop mode.
The DFLL has very short start-up time. When waking up from a sleep mode where the DFLL has
been turned off, and the DFLL clock was the main clock before going to sleep, the DFLL will be
re-enabled and start running with the same configuration as before going to sleep even if the ref-
erence clock is not available. The locks will not be lost. When the reference clock has restarted,
the FINE tracking will quickly compensate for any drift in frequency during sleep.
There are mainly three factors that decides the accuracy of the VCO frequency:
Due to multiple clock domains in the DFLLIF, values in configuration registers need to be syn-
chronized to other clock domains. Thus, before writing to a DFLLIF configuration register check
that the DFLL0RDY bit in PCLKSR register is high before writing. A write to a configuration reg-
ister while DFLL0RDY is low will be ignored.
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF contains an implementation defined
number of generic clocks that can provide a wide range of accurate clock frequencies.
• FINE resolution: The frequency step between two FINE values. Refer to the Electrical
• Reference frequency: The reference frequency should be below 100kHz for optimal accuracy
• The accuracy of the reference clock.
Characteristics chapter.
GCLK
Binary Sequence
Pseudorandom
Spread Spectrum
AMPLITUDE,
STEPSIZE
Generator
FINE
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To DAC
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