AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 710

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

30.7.2
Name:
Access Type:
Offset:
Reset Value:
• TRMIS: Transmit Mismatch
• OVERRUN: Data Overrun
• DREADYINT: Data Ready Interrupt
• READYINT: Ready Interrupt
• CENABLED: Clock Enabled
32099D–06/2010
31
23
15
7
-
-
-
-
0: No transfers mismatches.
1: The transceiver was active when receiving.
This bit is set when the transceiver is active when receiving.
This bit is cleared when corresponding bit in SCR is written to one.
0: No data overwritten in RHR.
1: Data in RHR has been overwritten before it has been read.
This bit is set when data in RHR is overwritten before it has been read.
This bit is cleared when corresponding bit in SCR is written to one.
0: No new data in the RHR.
1: New data received and placed in the RHR.
This bit is set when new data is received and placed in the RHR.
This bit is cleared when corresponding bit in SCR is written to one.
0: The interface has not generated an ready interrupt.
1: The interface has had a transition from busy to not busy.
This bit is set when the interface has transition from busy to not busy.
This bit is cleared when corresponding bit in SCR is written to one.
0: The aWire clock is not enabled.
1: The aWire clock is enabled.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x04
0x00000000
TRMIS
29
21
13
5
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
CENABLED
OVERRUN
26
18
10
2
-
-
AT32UC3L016/32/64
DREADYINT
25
17
9
1
-
-
-
READYINT
BUSY
24
16
8
0
-
-
710