AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 199

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.4.4
14.5.5
14.5.6
32099D–06/2010
Brown Out Detection (BOD)
Bandgap
Generic clock implementation
In AT32UC3L, there are six generic clocks. These are allocated to different functions as shown
in
Table 14-2.
Note:
The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply
voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default,
but can be enabled either by software or by flash fuses. The Brown-Out Detector can either gen-
erate an interrupt or a reset when the supply voltage is below the brown-out detection level. In
any case, the BOD output is available in bit PCLKSR.BODDET bit.
Note that any change to the BOD.LEVEL field of the BOD register should be done with the BOD
deactivated to avoid spurious reset or interrupt. When turned-on, the BOD output will be masked
during one half of a RCOSC clock cycle and two main clocks cycles to avoid false results.
If the JTAG or the AWIRE is enabled, the BOD reset and interrupt will be masked.
See Electrical Characteristics for parametric details.
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to those registers. To prevent unexpected writes due to software
bugs, write access to this register is protected by a locking mechanism, for details please refer to
the UNLOCK register description.
The Flash memory, the Brown-Out Detector (BOD) and the temperature sensor need a stable
voltage reference to operate. This reference voltage is provided by an internal Bandgap voltage
reference. This reference is automatically turned on at startup and turned off during DEEPSTOP
and STATIC sleep modes to save power.
The Bandgap voltage reference is calibrated through the BGCR.CALIB field. This field is loaded
after a Power On Reset with default values stored in factory-programmed flash fuses.
It is not recommended to override default factory settings as it may prevent correct operation of
the Flash and BOD. To prevent unexpected writes due to software bugs, write access to this
register is protected by a locking mechanism, for details please refer to the UNLOCK register
description.
Clock number
Table
5
0
1
2
3
4
1. GCLK5 is not routed out.
(1)
14-2. Note that only GCLK4-0 are routed out.
Generic clock allocation
Function
DFLLIF main reference and GCLK0 pin
(CLK_DFLLIF_REF)
DFLLIF dithering and ssg reference and GCLK1 pin
(CLK_DFLLIF_DITHER)
AST and GCLK2 pin
PWMA and GCLK3 pin
CAT, ACIFB and GCLK4 pin
GLOC
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