AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 133

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AT32UC3L064-D3HES

Manufacturer Part Number
AT32UC3L064-D3HES
Description
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
10.7.26
Name:
Access Type:
Offset:
Reset Value:
• LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset
32099D–06/2010
31
23
15
7
-
-
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one.
Performance Channel 1 Read Max Latency
30
22
14
6
-
-
PLATR1
Read/Write
0x824
0x00000000
29
21
13
5
-
-
28
20
12
4
-
-
LAT[15:8]
LAT[7:0]
27
19
11
3
-
-
26
18
10
2
-
-
AT32UC3L016/32/64
25
17
9
1
-
-
24
16
8
0
-
-
133

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