AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 509

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

23.7.2
23.7.3
23.7.4
23.7.5
23.8
23.8.1
32099D–06/2010
Functional Description
Power Management
Clocks
Interrupts
Debug Operation
Transfer Format
If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop
functioning and resume operation after the system wakes up from sleep mode. TWIS is able to
wake the system from sleep mode upon address match, see
The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state.
The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS
interrupts requires the interrupt controller to be programmed first.
When an external debugger forces the CPU into debug mode, the TWIS continues normal
operation. If the TWIS is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during
debugging.
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte
must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see
Figure 23-4 on page
Each transfer begins with a START condition and terminates with a STOP condition (see
ure 23-3 on page
Figure 23-3.
Figure 23-4. Transfer Format
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
TWD
TWCK
START and STOP Conditions
Start
509).
509).
Address
TWCK
TWD
R/W
Start
Ack
Data
Ack
AT32UC3L016/32/64
Section 23.8.7 on page
Data
Stop
Ack
Stop
516.
Fig-
509