AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 514

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 23-10. Slave Receiver with Multiple Data Bytes
23.8.5
32099D–06/2010
TCOMP
RXR DY
TWD
Using the Peripheral DMA Controller
S
DADR
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
slave to pull it down in order to generate the acknowledge. The master polls the data line dur-
ing this clock pulse.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 23-9. Slave Receiver with One Data Byte
The use of the Peripheral DMA Controller significantly reduces the CPU load. The program-
mer can set up ring buffers for the DMA controller, containing data to transmit or free buffer
space to place received data. By initializing NBYTES to 0 before a transfer, and setting
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordi-
5. If STOP is received, SR.TCOMP will be set.
6. If REPEATED START is received, SR.REP will be set.
R
NBYTES is decremented. NBYTES is usually configured to count downwards if PEC
is used.
nary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If
PEC is enabled and the last byte received was a PEC byte (indicated by NBYTES=0),
TWIS will automatically return an ACK if the PEC value was correct, otherwise a NAK
will be returned.
A
DATA n
TCOMP
RXR DY
TWD
A
Read RHR
S
DATA n
DATA (n+1)
DADR
A
DATA (n+1)
Read RHR
R
DAT A (n+m)-1
A
AT32UC3L016/32/64
DATA
DAT A (n+m)-1
A
Read RHR
DATA (n+m)
Read RHR
N
P
N
DATA (n+m)
Read RHR
P
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