AT32UC3L064-D3HES ATMEL [ATMEL Corporation], AT32UC3L064-D3HES Datasheet - Page 198

• Manufacturer Part Number: AT32UC3L064-D3HES
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.4.1
14.5.4.2
14.5.4.3
32099D–06/2010
Enabling a generic clock
Disabling a generic clock
Changing clock frequency
Each generic clock module runs from either clock source listed in the table on
page
clock can be independently enabled and disabled, and is also automatically disabled along with
peripheral clocks by the Sleep Controller in the Power Manager.
Figure 14-6. Generic clock generation
A generic clock is enabled by writing the CEN bit in GCCTRL to one. Each generic clock can
individually select a clock source by setting the OSCSEL bits. The source clock can optionally be
divided by writing DIVEN to one and the division factor to DIV, resulting in the output frequency:
The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables
the PB clocks. In either case, the generic clock will be switched off on the first falling edge after
the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still read
as one until the next falling edge occurs, and the clock is actually switched off. When writing
CEN to zero, the other bits in GCCTRL should not be changed until CEN reads as zero, to avoid
glitches on the generic clock.
When the clock is disabled, both the prescaler and output are reset.
When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.
235. The selected source can optionally be divided by any even integer up to 512. Each
f
GCLK
= f
SRC
OSCSEL
/
(2*(DIV+1))
Divider
DIV
DIVEN
0
1
AT32UC3L016/32/64
Sleep Controller
Mask
CEN
Generic Clock
Table 14-10 on
198