PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 315

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
No
PC = TOS
Q1
operation
operation
(TOS)
Return from subroutine. The stack is
Return from Subroutine
[ label ]
s
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, Status and BSR. If ‘s’ = 0,
no update of these registers occurs
(default).
1
2
RETURN
0000
No
No
Q2
[0,1]
W,
PC,
RETURN [s]
BSR,
0000
operation
Process
Status,
Data
No
Q3
0001
from stack
operation
Pop PC
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C, N, Z
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
1
1
RLCF
Read
0011
Q2
f
[0,1]
[0,1]
1110 0110
0
1110 0110
1100 1100
1
C
dest<0>
255
PIC18FXX8
dest<n + 1>,
C,
RLCF
01da
Process
Data
register f
Q3
REG, W
DS41159D-page 313
f [,d [,a]]
ffff
destination
Write to
Q4
ffff