PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 197

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

18.3.2
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register) or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
TABLE 18-9:
FIGURE 18-8:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend:
Note 1:
Name
RC7/RX/DT pin
RC6/TX/CK pin
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Read
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
PSPIE
PSPIP
PSPIF
SPEN
CSRC
Bit 7
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(1)
(1)
(1)
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
bit 0
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
bit 2
ADDEN
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
—
bit 3
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bit 4
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Bit 1
bit 5
TMR1IF
TMR1IE
TMR1IP
RX9D
TX9D
Bit 0
RBIF
bit 6
PIC18FXX8
0000 000x
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
DS41159D-page 195
bit 7
Q1 Q2 Q3 Q4
0000 000u
0000 0000
0000 0000
1111 1111
0000 000u
0000 0000
0000 -010
0000 0000
Value on
all other
Resets
‘0’