PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 191

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

18.2
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip dedicated 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The USART’s transmitter
and receiver are functionally independent but use the
same data format and baud rate. The Baud Rate
Generator produces a clock, either x16 or x64 of the bit
shift rate, depending on the BRGH bit (TXSTA regis-
ter). Parity is not supported by the hardware but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during Sleep.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver.
18.2.1
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one T
empty and flag bit TXIF (PIR1 register) is set. This
FIGURE 18-1:
 2004 Microchip Technology Inc.
USART Asynchronous Mode
USART ASYNCHRONOUS
TRANSMITTER
TXIE
Interrupt
TXEN
TXIF
USART TRANSMIT BLOCK DIAGRAM
Baud Rate Generator
CY
SPBRG
), the TXREG register is
Baud Rate CLK
MSb
(8)
TX9D
TSR Register
TX9
TXREG register
8
Data Bus
interrupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE1 register). Flag bit TXIF will be set
regardless of the state of enable bit TXIE and cannot be
cleared in software. It will reset only when new data is
loaded into the TXREG register. While flag bit, TXIF,
indicated the status of the TXREG register, another bit,
TRMT (TXSTA register), shows the status of the TSR
register. Status bit TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty.
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Note 1: The TSR register is not mapped in data
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
LSb
0
2: Flag bit TXIF is set when enable bit TXEN
TRMT
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
memory, so it is not available to the user.
is set.
and Control
Pin Buffer
SPEN
PIC18FXX8
RC6/TX/CK pin
DS41159D-page 189