PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 119

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

13.0
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to
Register 13-1 shows the Timer2 Control register.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON register) to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
REGISTER 13-1:
 2004 Microchip Technology Inc.
generate clock shift
TIMER2 MODULE
bit 7
bit 6-3
bit 2
bit 1-0
T2CON: TIMER2 CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
U-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
13.1
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (F
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON register). The match
output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, PIR
registers).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
TMR2 is not cleared when T2CON is written.
Watchdog Timer Reset or Brown-out Reset)
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Timer2 Operation
Timer2 is disabled on POR.
R/W-0
PIC18FXX8
OSC
/4) has a prescale option
T2CKPS1 T2CKPS0
x = Bit is unknown
R/W-0
DS41159D-page 117
R/W-0
bit 0