PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 250

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

20.5
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and the
Timer1 (or Timer3) counter will be reset to zero. Timer1
(or Timer3) is reset to automatically repeat the A/D
FIGURE 20-4:
TABLE 20-3:
DS41159D-page 248
PIC18FXX8
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH A/D Result Register
ADRESL
ADCON0
ADCON1
PORTA
TRISA
PORTE
LATE
TRISE
Legend:
Note 1:
Name
Use of the ECCP Trigger
GIE/GIEH PEIE/GIEL
PSPIF
PSPIE
PSPIP
A/D Result Register
ADCS1
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
These bits are reserved on PIC18F2X8 devices; always maintain these bits clear.
T
ADFM
Bit 7
CY
Set GO bit
IBF
—
—
—
—
—
—
—
Holding capacitor is disconnected from analog input
(typically 100 ns)
- T
(1)
(1)
(1)
SUMMARY OF A/D REGISTERS
AD
Conversion Starts
PORTA Data Direction Register
CMIE
CMIP
CMIF
ADCS0
ADCS2
T
A/D CONVERSION T
ADIF
ADIE
ADIP
AD
Bit 6
b9
OBF
RA6
—
—
1 T
(1)
(1)
(1)
AD
b8
TMR0IE
2 T
CHS2
RCIE
RCIP
IBOV
RCIF
Bit 5
RA5
—
—
—
—
—
—
AD
b7
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
3 T
PSPMODE
INT0IE
AD
b6
CHS1
Bit 4
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
RA4
—
—
—
4 T
AD
ADIF bit is set, holding capacitor is connected to analog input.
AD
CYCLES
b5
5 T
PCFG3
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
CHS0
Bit 3
RBIE
RA3
—
—
—
AD
b4
6 T
GO/DONE
TMR0IF
CCP1IE
CCP1IP
TRISE2
CCP1IF
PCFG2
LATE2
LVDIE
LVDIP
LVDIF
acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location). The
appropriate analog input channel must be selected and
the minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
Bit 2
AD
b3
RA2
RE2
7 T
AD
b2
TMR3IE ECCP1IE
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TRISE1
TMR2IF
TMR2IE
TMR2IP
PCFG1
8
INT0IF
LATE1
Bit 1
RA1
RE1
—
T
AD
b1
9 T
AD
TMR1IE
TMR1IP
TMR1IF
TRISE0
PCFG0
b0
LATE0
ADON
Bit 0
RBIF
RA0
RE0
10
 2004 Microchip Technology Inc.
T
AD
(1)
(1)
(1)
b0
11
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
-1-1 1111 -1-1 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
00-- 0000 00-- 0000
-x0x 0000 -u0u 0000
-111 1111 -111 1111
---- -xxx ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
POR, BOR
Value on
Value on
all other
Resets