KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 88

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Bank 47 PHY2 Special Control/Status Register (0x06): P2PHYCTRL
This register contains the control and status information of PHY2.
Bank 48 Port 1 Control Register 1 (0x00): P1CR1
This register contains the global per port control for the switch function.
Micrel, Inc.
August 2010
Bit
15-6
5
4
3
2
1
0
Bit
15-8
7
6
5
4-3
2
0
0
0
0
Default
0x00
0x0
Default
0x000
0
0
0
1
0
0
R/W
RO
RO
RO
RW
RW
RW
RW
R/W
RO
RW
RW
RW
RW
RW
Description
Reserved
Polarity reverse (polrvs)
1 = polarity is reversed.
0 = polarity is not reversed.
MDIX Status (mdix_st)
1 = MDI
0 = MDI-X
Force Link (force_lnk)
1 = force link pass.
0 = normal operation.
Power Saving (pwrsave)
1 = disable power saving.
0 = enable power saving.
Remote (Near-End) Loopback (rlb)
1 = perform remote loopback at Port 2's PHY(RXP2/RXM2 ->
TXP2/TXM2. see Figure 15)
0 = normal operation
Reserved
Description
Reserved
Broadcast Storm Protection Enable
1 = enable broadcast storm protection for ingress packets on the port.
0 = disable broadcast storm protection.
Diffserv Priority Classification Enable
1= enable DiffServ priority classification for ingress packets on the port.
0 = disable DiffServ function.
802.1p Priority Classification Enable
1= enable 802.1p priority classification for ingress packets on the port.
0 = disable 802.1p.
Port-Based Priority Classification
00 - ingress packets on port are classified as priority 0 queue if “DiffServ” or “802.1p” classification
is not enabled or fails to classify.
01 - ingress packets on port are classified as priority 1 queue if “DiffServ” or “802.1p” classification
is not enabled or fails to classify.
10 - ingress packets on port are classified as priority 2 queue if “DiffServ” or “802.1p” classification
is not enabled or fails to classify.
11 - ingress packets on port are classified as priority 3 queue if “Diffserv” or “802.1p” classification is
not enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of
802.1p and DSCP overwrites the port priority.
Tag Insertion
1 = when packets are output on the port, the switch adds 802.1p/q tags to packets without 802.1p/q
tags when received. The switch will not add tags to packets already tagged. The tag inserted is the
ingress port’s “port VID”.
0 = disable tag insertion.
88
Bit is same as:
Bank 51 0x04 bit 13
Bank 51 0x04 bit 7
Bank 51 0x00 bit 11
Bank 51 0x00 bit 10
Bank 51 0x00 bit 9
KSZ8862-16/32MQL
M9999-081310-3.1