KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 62

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Micrel, Inc.
August 2010
Bit
15-11
10
9
8
7
6
5
4
3
2
1
0
Bit
15-13
12-0
-
0x0
0x0
-
0x0
0x0
0x0
0x0
0x0
0x0
-
0x0
-
-
Default Value
Default Value
R/W
RO
RW
RW
RO
RW
RW
RW
RW
RW
RW
RO
RW
R/W
RO
RO
Description
Reserved
RXFCE Receive Flow Control Enable
When this bit is set, the KSZ8862M will acknowledge a PAUSE frame from the receive
interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE
frame control timer expires. When this bit is cleared, flow control is not enabled.
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue. When
reset, all CRC error frames are discarded.
Reserved
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
RXRA Receive All
When this bit is set, the KSZ8862M receives all incoming frames, regardless of the frame’s
destination address.
RXSCE Receive Strip CRC
When this bit is set, the KSZ8862M strips the CRC on the received frames. Once cleared,
the CRC is stored in memory following the packet.
QMU Receive Multicast Hash-Table Enable
When this bit is set, this bit enables the RX function to receive multicast frames that pass
the CRC Hash filtering mechanism.
Reserved
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state. When reset, the
receive process is placed in the stopped state upon completing reception of the current
frame.
Description
Reserved
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is used
for both frame payload, control word. There is total 4096 bytes in TXQ.
Note: Software must be written to ensure that there is enough memory for the next transmit
frame including control information before transmit data is written to the TXQ.
62
KSZ8862-16/32MQL
M9999-081310-3.1