KSZ8862 Micrel Semiconductor, KSZ8862 Datasheet
KSZ8862
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KSZ8862 Summary of contents
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... Ordering Information). This datasheet describes the KSZ8862M non-PCI CPU interface chip. The KSZ8862M is the industry’s first fully managed, 2- port switch with a non-PCI CPU interface and fiber support based on a proven, 4 integrated Layer-2 switch, compliant with IEEE 802.3u standards ...
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... Ordering Information). Additional Features In addition to offering all of the features of an integrated Layer-2 managed switch, the KSZ8862M offers: • Dynamic buffer memory scheme – Essential for applications such as Video over IP where image jitter is unacceptable • 2-port switch with a flexible 8, 16, or 32-bit generic host processor interfaces • ...
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... KSZ8862-16MQL- KSZ8862-32MQL- KSZ8862-32MQL- KSZ8862-32MQL- KSZ8862-100FX-EVAL Evaluation Board for the KSZ8862-16MQL at 100FX Mode KSZ8862-10FL-EVAL Evaluation Board for the KSZ8862-16MQL at 100SX_10FL Mode Revision History Revision Date 1.0 07/18/06 2.0 09/13/06 3.0 04/04/07 April 2007 Package o C 128-Pin PQFP o C 128-Pin PQFP ...
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... Markets.................................................................................................................................................................................2 Ordering Information ..........................................................................................................................................................3 Revision History..................................................................................................................................................................3 Pin Configuration for KSZ8862-16MQL (8/16-Bit) ..........................................................................................................11 Pin Description for KSZ8862-16MQL (8/16-Bit) ..............................................................................................................12 Pin Configuration for KSZ8862-32MQL (32-Bit) .............................................................................................................17 Pin Description for KSZ8862-32 MQL (32-Bit) ................................................................................................................18 Functional Description .....................................................................................................................................................23 Functional Overview: Physical Layer Transceiver ........................................................................................................23 100BASE-TX Transmit ...................................................................................................................................................23 100BASE-TX Receive ....................................................................................................................................................23 Scrambler/De-scrambler (100BASE-TX only) ................................................................................................................23 100BASE-FX Operation ...
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... Bank 2 Host MAC Address Register Low (0x00): MARL ...............................................................................................58 Bank 2 Host MAC Address Register Middle (0x02): MARM ..........................................................................................59 Bank 2 Host MAC Address Register High (0x04): MARH ..............................................................................................59 Bank 3 On-Chip Bus Control Register (0x00): OBCR ....................................................................................................59 Bank 3 EEPROM Control Register (0x02): EEPCR .......................................................................................................60 April 2007 5 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Bank 44 Digital Testing Control Register (0x04): DTCR ................................................................................................80 Bank 44 Analog Testing Control Register 0 (0x06): ATCR0 ..........................................................................................80 Bank 44 Analog Testing Control Register 1 (0x08): ATCR1 ..........................................................................................80 Bank 44 Analog Testing Control Register 2 (0x0A): ATCR2..........................................................................................80 Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR .........................................................................80 April 2007 6 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Operating Ratings ........................................................................................................................................................109 (1) Electrical Characteristics ............................................................................................................................................110 Timing Specifications .....................................................................................................................................................111 Asynchronous Timing without using Address Strobe (ADSN = 0) ...............................................................................111 Asynchronous Timing Using Address Strobe (ADSN) .................................................................................................112 Asynchronous Timing Using DATACSN.......................................................................................................................113 April 2007 ® (0x00): P1SCSLMD ..................................................................95 ® (0x00): P2SCSLMD ..................................................................98 7 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Synchronous Timing in Burst Read (VLBUSN = 1) ......................................................................................................116 Synchronous Write Timing (VLBUSN = 0)....................................................................................................................117 Synchronous Read Timing (VLBUSN = 0) ...................................................................................................................118 EEPROM Timing ..........................................................................................................................................................119 Auto Negotiation Timing ...............................................................................................................................................120 Reset Timing.................................................................................................................................................................121 Selection of Isolation Transformers..............................................................................................................................122 Selection of Reference Crystal ......................................................................................................................................122 Package Information.......................................................................................................................................................123 Acronyms and Glossary.................................................................................................................................................124 April 2007 8 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Figure 7. Destination Address Lookup Flow Chart in Stage One .......................................................................................................... 30 Figure 8. Destination Address Resolution Flow Chart in Stage Two ..................................................................................................... 31 Figure 9. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8862M Bus ......................................................... 36 Figure 10. KSZ8862M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections................................................................................................. 37 Figure 11. 802.1p Priority Field Format .................................................................................................................................................. 44 Figure 12 ...
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... Table 31. Synchronous Read (VLBUSN = 0) Timing Parameters ....................................................................................................... 118 Table 32. EEPROM Timing Parameters.............................................................................................................................................. 119 Table 33. Auto Negotiation Timing Parameters................................................................................................................................... 120 Table 34. Reset Timing Parameters .................................................................................................................................................... 121 Table 35. Transformer Selection Criteria............................................................................................................................................. 122 Table 36. Qualified Single Port Magnetic ............................................................................................................................................ 122 Table 37. Typical Reference Crystal Characteristics ........................................................................................................................... 122 April 2007 10 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Micrel, Inc. Pin Configuration for KSZ8862-16MQL (8/16-Bit) April 2007 Figure 2. 128-Pin PQFP (Top View) 11 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extended accesses. For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8862M drives this pin low to signal wait states. Opd Interrupt ...
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... Opd Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 decode to the KSZ8862M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Ipd Read Strobe Not Asynchronous read strobe, active Low ...
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... Set physical transmits output current. Pull-down this pin with a 3.01K 1% resistor to ground. Gnd Analog ground P 1.2V analog V for PLL input power supply from VDDCO (pin24) through external DD Ferrite bead and capacitor. Gnd Analog ground I 25MHz crystal or oscillator clock connection. 14 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... IO with well decoupling capacitors. DDIO I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect I No Connect 15 KSZ8862-16/32MQL 50ppm for either crystal or oscillator. M9999-040407-3.0 ...
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... IO with well decoupling capacitors. DDIO I No Connect I/O Data 15 I/O Data 14 I/O Data 13 I/O Data 12 I/O Data 11 I/O Data 10 I/O Data 9 I/O Data 8 I/O Data 7 I/O Data 6 I/O Data 5 I/O Data 4 I/O Data 3 Gnd Digital IO ground Gnd Digital core ground P 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO I/O Data 2 I/O Data 1 I/O Data 0 16 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Micrel, Inc. Pin Configuration for KSZ8862-32MQL (32-Bit) April 2007 Figure 3. 128-Pin PQFP (Top View) 17 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend accesses. For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8862M drives this pin low to signal wait states. Interrupt 18 KSZ8862-16/32MQL [0,1] — ...
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... Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 decode to the KSZ8862M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not Asynchronous read strobe, active Low ...
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... Pins (X1, X2) connect to a crystal oscillator is used, X1 connects to a 3.3V tolerant oscillator and connect. Note: Clock is 50ppm for either crystal or oscillator. Hardware reset pin (active Low). This reset input is required minimum of 10ms low after stable supply voltage 3.3V. Address 15 20 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... IO with well decoupling capacitors. DDIO Data 30 Data 29 Data 28 Data 27 Data 26 Data 25 Data 24 Data 23 Data 22 Data 21 Data 20 Data 19 Data 18 Data 17 Digital IO ground 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 16 Data 15 21 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Opu = Output with internal pull-up April 2007 Pin Function Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data 7 Data 6 Data 5 Data 4 Data 3 Digital IO ground Digital core ground 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO Data 2 Data 1 Data 0 22 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... The KSZ8862M contains two 10/100 physical layer transceivers (PHYs), two MAC units, and a DMA channel integrated with a Layer-2 switch. The KSZ8862M contains a bus interface unit (BIU), which controls the KSZ8862M via an 8, 16, or 32-bit host interface. Physical signal transmission and reception are enhanced through the use of analog circuits in the PHY that make the design more efficient and allow for low power consumption ...
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... A far-end-fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KSZ8862M detects a FEF when its FXSD1 input on port 1 is between 1V and 1.8V. When a FEF is detected, the KSZ8862M signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames. ...
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... RXM1 or 16mV (rms) for 100Base-SX receive on pin RXM1. Power Management The KSZ8862M features per port power-down mode. To save power, the user can power-down the port that is not in use by setting bit 11 in either P1CR4 or P1MBCR register for port 1 and setting bit 11 in either P2CR4 or P2MBCR register for port 2 ...
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... (RJ-45 tch) Figure 5. Typical Crossover Cable Connection 26 KSZ8862-16/32MQL 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair 5 ...
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... If auto negotiation is not supported or the link partner to the KSZ8862M is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... If P2VCT [14:13] =11, this indicates an invalid test, and occurs when the KSZ8862M is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8862M to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...
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... The internal lookup table stores MAC addresses and their associated information. It contains a 1K entry unicast address learning table plus switching information. The KSZ8862M is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables, which depending upon the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn ...
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... Micrel, Inc. Forwarding The KSZ8862M forwards packets using the algorithm that is depicted in the following flowcharts. Figure 7 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “ ...
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... These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. The KSZ8862M intercepts these packets and performs the flow control. 3. "Local" packets. Based on destination address (DA) look-up. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as " ...
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... KSZ8862M issues a flow control frame (Xoff), containing the maximum pause time as defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8862M then sends out the other flow control frame (Xon) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated ...
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... In terms of physical data bus size, the KSZ8862M supports 8, 16, and 32 bit host/industrial standard data bus sizes. Given a physical data bus size, the KSZ8862M supports 8, 16, or 32-bit data transfers depending upon the size of the physical data bus. For example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (KSZ8862- 32MQL) ...
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... Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low because 32 bit transfers are assumed. Note 2: BE2N and BE3N are valid only for the KSZ8862-32 mode, and are NC for the KSZ8862-16 mode. Data For KSZ8862-32 Mode only Data For both KSZ8862-32 and KSZ8862-16 Modes Address Strobe The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N and BE0N ...
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... EISA-like bus (non-burst) interface as shown in the Figure 17. This type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and qualifies with AEN to determine if the KSZ8862M switch is the intended target. The data transfer is the same as the first case. ...
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... SRDYN The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched the read data. The KSZ8862M holds the read data until RDYRTNN is asserted. The timing waveform is shown in Figure 22 and Figure 23. For EISA-like burst transfer interface (VLBUSN = 1): The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to indicate the burst write. Note that in this application, both the system/host/memory and KSZ8862M are capable of inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal ...
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... Figure 10. KSZ8862M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections BIU Implementation Principles Since the KSZ8862M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-A4 and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is assumed (BE3N – BE0N are ignored). ...
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... Each control word corresponds to one TX packet. Table 4 gives the transmit control word bit fields. Bit Description 15 TXIC Transmit Interrupt on Completion When bit is set, the KSZ8862M sets the transmit interrupt after the present frame has been transmitted. 14-10 Reserved 9-8 TXDPN Transmit Destination Port Number When bit is set, this field indicates the destination port(s) where the packet is forwarded from host system ...
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... On transmit, all bytes are provided by the CPU, including the source address. The KSZ8862M does not insert its own source address. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the KSZ8862M treated transparently as data for transmit operations. ...
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... Table 8 gives the format of the RX byte count field. Bit Description 15-11 Reserved 10-0 RXBC Receive Byte Count Receive Byte Count. April 2007 Table 7. FRXQ Packet Receive Status Table 8. FRXQ RX Byte Count Field 40 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. Address learning is enabled on the port in this state. Table 9. Spanning Tree States 41 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... SGCR2, bit 8 to “1”. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be “transmit sniff”, and the host port is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8862M forwards the packet to both port 2 and the host port. ...
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... The KSZ8862M supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8862M provides a 16-entry VLAN table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN table lookup to determine whether the VID is valid ...
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... DSCP register to determine priority. Rate Limiting Support The KSZ8862M supports hardware rate limiting from 64 Kbps to 88 Mbps, independently on the “receive side” and on the “transmit side” per port basis. For 10-base T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers ...
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... The KSZ8862M operates only as a managed switch. EEPROM Interface It is optional in the KSZ8862M to use an external EEPROM. In the case that an EEPROM is not used, the EEEN pin must be tied Low or floating. The external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address, base address, and default configuration settings ...
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... Figure 12. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of the KSZ8862M. The loopback path starts at the PHY port receiving inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’ ...
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... Figure 13. Port 1 and port 2 Near-End (Remote) Loopback Path 47 KSZ8862-16/32MQL ...
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... Micrel, Inc. CPU Interface I/O Registers The KSZ8862M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets by reading and writing through the packet data registers ...
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... Address High Info [7:0] [7:0] Reserved RX Host MAC Memory BIST Address High Info [15:8] [15:8] Global Reset [7:0] Reserved Reserved Global Reset [15:8] Bus Configuration [7:0] Reserved Reserved Bus Configuration [15:8] 49 Bank 4 Bank 5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] KSZ8862-16/32MQL Bank 6 Bank 7 M9999-040407-3.0 ...
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... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF April 2007 Bank Location Bank 9 Bank 10 Bank 11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 50 KSZ8862-16/32MQL Bank 12 Bank 13 Bank 14 M9999-040407-3.0 Bank 15 ...
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... RX Frame Receive Byte Multicast Data Pointer Counter Table 3 [15:8] [15:8] [15:8] QMU Data Low [7:0] Reserved Reserved QMU Data Low [15:8] QMU Data High [7:0] QMU Data High [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 51 KSZ8862-16/32MQL Bank 20 Bank 21 Bank 22 Reserved Reserved Reserved Reserved Reserved Reserved M9999-040407-3.0 Bank 23 ...
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... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF April 2007 Bank Location Bank 25 Bank 26 Bank 27 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 52 KSZ8862-16/32MQL Bank 28 Bank 29 Bank 30 M9999-040407-3.0 Bank 31 ...
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... Bank Location Bank 33 Bank 34 Bank 35 Switch Global Control 6 [7:0] Switch Global Control 6 [15:8] Switch Global Control 7 [7:0] Switch Global Control 7 [15:8] Reserved Bank Select [7:0] Bank Select [15:8] 53 KSZ8862-16/32MQL Bank 36 Bank 37 Bank 38 Reserved Reserved Reserved Reserved Reserved Reserved M9999-040407-3.0 Bank 39 MAC Address 1 [7:0] MAC Address 1 [15:8] MAC Address 2 ...
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... Reserved Reserved Indirect Access Data 4 [15:8] Indirect Access Data 5 [7:0] Reserved Reserved Indirect Access Data 5 [15:8] Bank Select [7:0] Bank Select [15:8] 54 KSZ8862-16/32MQL Bank 44 Bank 45 Bank 46 Digital Test PHY1 MII- PHY2 MII- Status Register Register Basic Control Basic Control [7:0] [7:0] [7:0] Digital Test PHY1 MII- PHY2 MII- ...
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... Reserved Reserved Port2 Ingress Rate Control [15:8] Port2 Egress Rate Control [7:0] Reserved Reserved Port2 Egress Rate Control [15:8] Bank Select [7:0] Bank Select [15:8] 55 KSZ8862-16/32MQL Bank 52 Bank 53 Bank 54 Host Port Control 1 [7:0] Reserved Host Port Control 1 [15:8] Host Port Control 2 [7:0] Reserved Host Port Control 2 [15:8] ...
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... To 0xB 0xA 0xA - 0xB 0xB 0xC 0xC - 0xD 0xD 0xC To 0xF 0xE 0xE - 0xF 0xF April 2007 Bank Location Bank 57 Bank 58 Bank 59 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bank Select [7:0] Bank Select [15:8] 56 KSZ8862-16/32MQL Bank 60 Bank 61 Bank 62 M9999-040407-3.0 Bank 63 ...
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... Description BARH Base Address High These bits are compared against the address on the bus ADDR[15:8] to determine the BASE for the KSZ8862M registers. BARL Base Address Low These bits are compared against the address on the bus ADDR[7:5] to determine the BASE for the KSZ8862M registers. ...
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... MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3) MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5) The Host MAC address is used to define the individual destination address that the KSZ8862M responds to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101 ...
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... Bank 3 On-Chip Bus Control Register (0x00): OBCR This register controls the on-chip bus speed for the KSZ8862M used for power management when the external host CPU is running at a slow frequency. The default of the on-chip bus speed is 125 MHz without EEPROM. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance ...
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... EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are loaded from the EEPROM immediately after reset. The KSZ8862M allows the software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is set ...
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... Note: Setting this bit requires enabling the ADD CRC feature to avoid CRC errors for the transmit packet. TXCE Transmit CRC Enable When this bit is set, the KSZ8862M automatically adds a CRC checksum field to the end of a transmit frame. TXE Transmit Enable When this bit is set, the transmit module is enabled and placed in a running state. When reset, the transmit process is placed in the stopped state after the transmission of the current frame is completed ...
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... When this bit is set, the KSZ8862M receives all incoming frames, regardless of the frame’s destination address. RXSCE Receive Strip CRC When this bit is set, the KSZ8862M strips the CRC on the received frames. Once cleared, the CRC is stored in memory following the packet. QMU Receive Multicast Hash-Table Enable When this bit is set, this bit enables the RX function to receive multicast frames that pass the CRC Hash filtering mechanism ...
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... When this bit is reset, the TX frame data pointer is manually controlled by user to access the TX frame location. Reserved TXFP TX Frame Pointer TX Frame Pointer index to the Frame Data register for access. This field reset to next available TX frame location when the TX Frame Data has been enqueued through the TXQ command register. 63 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... This register is mapped into two uni-directional buffers for 16-bit buses, and one uni- directional buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and from the KSZ8862M regardless of whether the pointer is even, odd, or Dword aligned. Byte, word, and Dword access can be mixed on the fly in any order. This register along with DQRH is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate Dword move operations ...
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... When this bit is set, the Receive Process Stopped interrupt is enabled. When this bit is reset, the Receive Process Stopped interrupt is disabled. RXEFIE Receive Error Frame Interrupt Enable When this bit is set, the Receive error frame interrupt is enabled. When this bit is reset, the Receive error frame interrupt is disabled. Reserved 65 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... This edge-triggered interrupt status is cleared by writing 1 to this bit. RXEFIE Receive Error Frame Interrupt Status When this bit is set, it indicates that the Receive error frame status has occurred. This edge-triggered interrupt status is cleared by writing 1 to this bit. Reserved 66 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... When set, it indicates that a CRC error has occurred on the current received frame. A CRC error frame is passed to the host only if the pass bad frame bit is set (bit 9 in RXCR register). Description Reserved RXBC Receive Byte Count Receive Byte Count. 67 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all multicast addresses are received regardless of the multicast table value. 68 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... April 2007 Description Family ID Chip family ID Chip ID 0x8 is assigned to KSZ8862M Revision ID Start Switch 1 = start the chip switch is disabled. Description Pass All Frames 1 = switch all packets including bad ones. Used solely for debugging purposes. Works in conjunction with Sniffer mode only. ...
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... RW Huge Packet Support 1 = accepts packet sizes up to 1916 bytes (inclusive). This bit setting overrides setting from bit 1 of the same register the max packet size is determined by bit 1 of this register. April 2007 70 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... The period is 67ms for 100BT or 670ms for 10BT. The default is 1%. Rate: 148,800 frames/sec * 67 ms/interval * frames/interval (approx.) = 0x63. Bank 32 Switch Global Control Register 4 (0x08): SGCR4 This register contains the global control for the switch function. Bit Default R/W Description 15-0 0x2400 RW Reserved April 2007 71 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Port n LED indicators, (where for port 1 and n =2 for port 2) defined as below: PnLED3 PnLED2 PnLED1 PnLED0 PnLED3 PnLED2 PnLED1 PnLED0 Reserved 7-0 0x35 RW Reserved April 2007 [LEDSEL1, LEDSEL0] [0, 0] [0, 1] ------ ------ LINK/ACT 100LINK/ACT FULL_DPX/COL 10LINK/ACT SPEED FULL_DPX [LEDSEL1, LEDSEL0] [1, 0] [1, 1] ACT ------ LINK ------ FULL_DPX/COL ------ SPEED ------ 72 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Unknown Packet Default Port(s) Specify which ports to send packets with unknown destination addresses. Feature is enabled by bit [7]. Bit 2 for the host port, bit 1 for port 2, and bit 0 for port 1 Banks 34 – 38: Reserved Except Bank Select Register (0xE) April 2007 73 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Class value is 0x08. 3-2 0 R/W DSCP[3:2] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x04. 1-0 0 R/W DSCP[1:0] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x00. April 2007 74 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Class value is 0x48. DSCP[35:34] 3-2 0 R/W The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x44. 1-0 0 R/W DSCP[33:32] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x40. April 2007 75 KSZ8862-16/32MQL M9999-040407-3.0 ...
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... Class value is 0x8c. 5-4 0 R/W DSCP[69:68] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x88. 3-2 0 R/W DSCP[67:66] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x84. April 2007 76 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 77
... Class value is 0xd4. DSCP[105:104] 9-8 0 R/W The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xd0. 7-6 0 R/W DSCP[103:102] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xcc. April 2007 77 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 78
... This register contains the indirect control for the switch function. Bit Default R/W Description 15-13 0x0 RW Reserved Read High. Write Low 1 = read cycle write cycle. Table Select 11-10 0x0 static MAC address table selected VLAN table selected dynamic address table selected MIB counter selected. April 2007 78 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 79
... Bit 15-0 of indirect data. Bank 42 Indirect Access Data Register 5 (0x0A): IADR5 This register contains the indirect data for the switch function. Bit Default R/W Description 15-0 0x0000 RW Indirect Data Bit 31-16 of indirect data. Bank 43: Reserved Except Bank Select Register (0xE) April 2007 79 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 80
... This register contains Media Independent Interface (MII) register for switch port 1 as defined in the IEEE 802.3 specification. Bit Default R/W Description Soft reset Not supported Far-End Loopback 1 = perform loopback as follows: April 2007 Start: RXP2/RXM2 (port 2) Loop back: PMD/PMA of port 1’s PHY End: TXP2/TXM2 (port 2) 80 KSZ8862-16/32MQL Bit is same as: Bank 49 0x02 bit 8 M9999-040407-3.0 ...
Page 81
... April 2007 Bit is same as: Bank 49 0x02 bit 6 Bank 49 0x02 bit 7 Bank 49 0x02 bit 11 Bank 49 0x02 bit 13 Bank 49 0x02 bit 5 Bank 49 0x04 bit 15 Bank 49 0x02 bit 9 Bank 49 0x02 bit 10 Bank 49 0x02 bit 12 Bank 49 0x02 bit 14 Bank 49 0x02 bit 15 81 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 82
... Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR This register contains the PHY ID (high) for the switch port 1 function. Bit Default R/W Description 15-0 0x0022 RO PHYID High High order PHYID bits. April 2007 Bit is same as: Bank 49 0x04 bit 6 Bank 49 0x04 bit 8 Bank49 0x04 bit 5 82 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 83
... Reserved April 2007 Bit is same as: Bank 49 0x02 bit 4 Bank49 0x02 bit 3 Bank49 0x02 bit 2 Bank49 0x02 bit 1 Bank49 0x02 bit 0 Bit is same as: Bank 49 0x04 bit 4 Bank 49 0x04 bit 3 Bank 49 0x04 bit 2 Bank 49 0x04 bit 1 Bank 49 0x04 bit 0 83 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 84
... LED normal operation. April 2007 Start: RXP1/RXM1 (port 1) Loop back: PMD/PMA of port 2’s PHY End: TXP1/TXM1 (port 1) 84 KSZ8862-16/32MQL Bit is same as: Bank 51 0x02 bit 8 Bank 51 0x02 bit 6 Bank 51 0x02 bit 7 Bank 51 0x02 bit 11 Bank 51 0x02 bit 13 Bank 51 0x02 bit 5 ...
Page 85
... Bank 46 PHY 2 PHYID High Register (0x06): PHY2IHR This register contains the PHY ID (high) for the switch port 2 function. Bit Default R/W Description 15-0 0x0022 RO PHYID High High order PHYID bits. April 2007 Bit is same as: Bank 51 0x04 bit 6 Bank 51 0x04 bit 8 Bank 51 0x04 bit 5 85 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 86
... Reserved April 2007 Bit is same as: Bank 51 0x02 bit 4 Bank 51 0x02 bit 3 Bank 51 0x02 bit 2 Bank 51 0x02 bit 1 Bank 51 0x02 bit 0 Bit is same as: Bank 51 0x04 bit 4 Bank 51 0x04 bit 3 Bank 51 0x04 bit 2 Bank 51 0x04 bit 1 Bank 51 0x04 bit 0 86 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 87
... RO Vct_fault_count Distance to the fault. The distance is approximately 0.4m*vct_fault_count. April 2007 ® control and status information of PHY 2. 87 KSZ8862-16/32MQL Bit is same as: Bank 49 0x04 bit 13 Bank 49 0x04 bit 7 Bank 49 0x00 bit 11 Bank 49 0x00 bit 10 Bank 49 0x00 bit 9 Bit is same as: Bank 51 0x00 bit 12 ...
Page 88
... The switch will not add tags to packets already tagged. The tag inserted is the ingress port’s “port VID” disable tag insertion. April 2007 Bit is same as: Bank 51 0x04 bit 13 Bank 51 0x04 bit 7 Bank 51 0x00 bit 11 Bank 51 0x00 bit 10 Bank 51 0x00 bit 9 88 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 89
... RW Transmit Sniff 1 = all packets transmitted on the port are marked as “monitored packets” and forwarded to the designated “sniffer port.” transmit monitoring Reserved April 2007 89 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 90
... Ingress and Egress rate limiting calculations. 0= IFG bytes are not counted Count Preamble Count preamble Bytes each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations preamble bytes are not counted. April 2007 90 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 91
... Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). 7-4 0x0 RW Ingress Pri1 Rate Priority 1 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = Not limited (default) 0001 = 64Kbps 0010 = 128Kbps 0011 = 256Kbps 0100 = 512Kbps 0101 = 1Mbps 0110 = 2Mbps 0111 = 4Mbps April 2007 91 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 92
... Mbps 1101 = 72Mbps 1110 = 80Mbps 1111 = 88Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). April 2007 92 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 93
... Egress Pri1 Rate Egress data rate limit for priority 1 frames. Output traffic from this priority queue is shaped according to the egress rate selected below: 0000 = Not limited (default) 0001 = 64Kbps 0010 = 128Kbps 0011 = 256Kbps 0100 = 512Kbps 0101 = 1Mbps April 2007 93 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 94
... Notes: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited). When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. April 2007 94 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 95
... End: TXP2/TXM2 (port 2 normal operation Auto Negotiation Enable (Note 1) April 2007 ® (0x00): P1SCSLMD 95 KSZ8862-16/32MQL Bit is same as: Bank 47 0x02 bit 3 Bank 47 0x02 bit 2 Bank 47 0x02 bit 1 Bit is same as: Bank 45 0x00 bit 0 Bank 45 0x00 bit1 Bank 45 0x00 bit 9 Bank 45 0x00 bit 2 ...
Page 96
... RO Operation Duplex 1 = link duplex is full. April 2007 96 KSZ8862-16/32MQL Bit is same as: Bank 45 0x00 bit 13 Bank 45 0x00 bit 8 Bank 45 0x08 bit 10 Bank 45 0x08 bit 8 Bank 45 0x08 bit 7 Bank 45 0x08 bit 6 Bank 45 0x08 bit 5 Bit is same as: ...
Page 97
... This register contains per port ingress rate control. See description in P1IRCR, Bank 48 (0x08) Bank 50 Port 2 Egress Rate Control Register (0x0A): P2ERCR This register contains per port egress rate control. See description in P1ERCR, Bank 48 (0x0A) April 2007 97 KSZ8862-16/32MQL Bit is same as: Bank 45 0x02 bit 4 Bank 47 0x02 bit 4 Bank 45 0x02 bit 5 ...
Page 98
... RO Vct_fault_count VCT fault count. The distance to the fault is approximately 0.4m*vct_fault_count. April 2007 ® (0x00): P2SCSLMD 98 KSZ8862-16/32MQL Bit is same as: Bank 47 0x04 bit 12 Bank 47 0x04 bit 14-13 Bank 47 0x04 bit 15 Bank 47 0x06 bit 3 Bank 47 0x06 bit 2 Bank 47 0x06 bit 1 Bank 47 0x04 bit 8-0 ...
Page 99
... RW Advertised 100BT half-duplex capability advertise 100BT half-duplex capability suppress 100BT half-duplex capability from transmission to the link partner. April 2007 99 KSZ8862-16/32MQL Bit is same as: Bank 46 0x00 bit 0 Bank 46 0x00 bit 1 Bank 46 0x00 bit 9 Bank 46 0x00 bit 2 Bank 46 0x00 bit 11 Bank 46 0x00 bit 3 ...
Page 100
... RO Partner 100BT full-duplex capability link partner 100BT full-duplex capable link partner not 100BT full-duplex capable. April 2007 100 KSZ8862-16/32MQL Bit is same as: Bank 46 0x08 bit 6 Bank 46 0x08 bit 5 Bit is same as: Bank 46 0x00 bit 5 Bank 47 0x06 bit 5 Bank 46 0x02 bit 4 Bank 47 0x06 bit 4 ...
Page 101
... Reserved User Priority Ceiling the packet’s “user priority field” is greater than the “user priority field” in the port default tag April 2007 101 KSZ8862-16/32MQL Bit is same as: Bank 46 0x0A bit 7 Bank 46 0x0A bit 6 Bank 46 0x0A bit 5 M9999-040407-3.0 ...
Page 102
... This register contains per port ingress rate control. See description in P1IRCR, Bank 48 (0x08) Bank 52 Host Port Egress Rate Control Register (0x0A): P3ERCR This register contains per port egress rate control. See description in P1ERCR, Bank 48 (0x0A) Banks 53 – 63: Reserved Except Bank Select Register (0xE) April 2007 102 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 103
... MIB (Management Information Base) Counters The KSZ8862M provides 34 MIB counters for each port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 14 and “all ports dropped packet” as shown in Table 16 ...
Page 104
... Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 15. Port 1 MIB Counters Indirect Memory Offset Description Reserved Counter Value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 104 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 105
... All Ports Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters. April 2007 // If bit restart (reread) from this register // If bit restart (reread) from this register 105 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 106
... The static DA look up result takes precedence over the dynamic DA look up result. If there match in both tables, the result from the static table is used. These entries in the static table will not be aged out by the KSZ8862M. Bit ...
Page 107
... Time Stamp Specifies the 2-bit counter for internal aging. Source port Identifies the source port where FID+MAC is learned: 00: port 1 01: port 2 10: port 3 FID Specifies the filter ID. MAC Address Specifies the 48-bit MAC address. 107 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 108
... R/W If 802.1Q VLAN mode is enabled, then the KSZ8862M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, then the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place ...
Page 109
... No (HS) heat spreader in this package. The θJA is under air velocity 1 m/s. April 2007 (1) Pins VDDATX, VDDARX, VDDIO All Inputs All Outputs N/A N/A Table 21. Maximum Ratings Min 3.1V 3.1V 0° Table 22. Operating Ratings 109 KSZ8862-16/32MQL Value –0.5V to 4.0V –0. –0.5V to 4.0V — –55°C to 150°C Typ Max 3.3V 3.5V 3.3V 3.5V 70°C 125°C 37.5 °C/W M9999-040407-3.0 ...
Page 110
... Peak to peak I (+/- 5%) VDDATX, VDDARX, VDDIO = 3. RMS 10FL V RMS 100SX 5MHz square wave V sq Table 23. Electrical Characteristics 110 KSZ8862-16/32MQL Min Typ Max 153mA 97mA 2.0V 0.8V -10µA 10µA 2.4V 0.4V 10µA +0.95V +1.05V 2% 3ns 5ns 0ns 0.5ns +0 ...
Page 111
... Note2: In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail. Table 24. Asynchronous Cycle (ADSN = 0) Timing Parameters April 2007 valid Figure 14. Asynchronous Cycle – ADSN = 0 111 KSZ8862-16/32MQL valid t5 t6 valid t8 t10 ...
Page 112
... A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail. Table 25. Asynchronous Cycle using ADSN Timing Parameters April 2007 t8 valid t10 Figure 15. Asynchronous Cycle – Using ADSN 112 KSZ8862-16/32MQL valid valid t2 t9 t11 Min Typ Max ...
Page 113
... Note2: In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail. Table 26. Asynchronous Cycle using DATACSN Timing Parameters April 2007 Figure 16. Asynchronous Cycle – Using DATACSN 113 KSZ8862-16/32MQL t2 valid valid t8 t10 Min ...
Page 114
... A1-A15, AEN, BExN[3:0] setup to ADSN t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising t3 A4-A15, AEN to LDEVN delay April 2007 t1 t3 Figure 17. Address Latching Cycle for All Modes Table 27. Address Latching Timing Parameters 114 KSZ8862-16/32MQL t2 Min Typ Max Unit ...
Page 115
... SRDYN hold to BCLK rising t10 DATACSN hold to BCLK rising t11 SWR hold to BCLK falling t12 CYCLEN hold to BCLK rising April 2007 Figure 18. Synchronous Burst Write Cycles – VLBUSN = 1 Table 28. Synchronous Burst Write Timing Parameters 115 KSZ8862-16/32MQL Min Typ Max Unit ...
Page 116
... SWR hold to BCLK falling t12 CYCLEN hold to BCLK rising April 2007 data0 Figure 19. Synchronous Burst Read Cycles – VLBUSN = 1 Table 29. Synchronous Burst Read Timing Parameters 116 KSZ8862-16/32MQL t10 t11 t12 data1 data2 data3 Min Typ Max Unit ...
Page 117
... SRDYN hold to BCLK t11 RDYRTNN setup to BCLK t12 RDYRTNN hold to BCLK Table 30. Synchronous Write (VLBUSN = 0) Timing Parameters April 2007 t2 valid t1 t5 Figure 20. Synchronous Write Cycle – VLBUSN = 0 117 KSZ8862-16/32MQL valid t9 t10 t11 t12 Min Typ Max Unit ...
Page 118
... RDYRTNN setup to BCLK rising t11 RDYRTNN hold after BCLK rising Table 31. Synchronous Read (VLBUSN = 0) Timing Parameters April 2007 t2 valid Figure 21. Synchronous Read Cycle – VLBUSN = 0 118 KSZ8862-16/32MQL t7 t6 valid t8 t9 t10 t11 Min Typ Max Unit 4 ns ...
Page 119
... April 2007 tcyc D15 Figure 22. EEPROM Read Cycle Timing Diagram Min Typ 4 (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 0.8 (OBCR[1:0]=00 on-chip bus speed @ 125 MHz Table 32. EEPROM Timing Parameters 119 KSZ8862-16/32MQL D0 D1 D13 D14 Max Unit µ M9999-040407-3.0 ...
Page 120
... Clock pulse to CTD data pulse t Clock pulse to CTC clock pulse Number of Clock/Data pulses per burst April 2007 Figure 23. Auto-Negotiation Timing Min Typ 100 55.5 64 111 128 17 Table 33. Auto Negotiation Timing Parameters 120 KSZ8862-16/32MQL Max Unit 69.5 µs 139 µs 33 M9999-040407-3.0 ...
Page 121
... Micrel, Inc. Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8862M supply voltage (3.3V). The reset timing requirement is summarized in the Figure 26 and Table 34. Symbol Parameter Stable supply voltages to reset High ...
Page 122
... Part Number H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S Table 36. Qualified Single Port Magnetic Value 25 ± Table 37. Typical Reference Crystal Characteristics 122 KSZ8862-16/32MQL Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Auto MDI-X Number of Port Yes 1 Yes 1 Yes 1 Yes 1 ...
Page 123
... Micrel, Inc. Package Information April 2007 Figure 25. 128-Pin PQFP Package 123 KSZ8862-16/32MQL M9999-040407-3.0 ...
Page 124
... An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' 124 KSZ8862-16/32MQL . CRC for M9999-040407-3.0 ...
Page 125
... A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. 125 KSZ8862-16/32MQL M9999-040407-3.0 ...