KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 18

• Manufacturer Part Number: KSZ8862-16_10
• Description: 2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
• Manufacturer: MICREL [Micrel Semiconductor]

Pin Description for KSZ8862-32 MQL (32-Bit)
Micrel, Inc.
August 2010
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Name
TEST_EN
SCAN_EN
P1LED2
P1LED1
P1LED0
P2LED2
P2LED1
P2LED0
DGND
VDDIO
RDYRTNN
BCLK
DATACSN
NC
SRDYN
Type
I
I
Opu
Opu
Opu
Opu
Opu
Opu
Gnd
P
Ipd
Ipd
Ipu
Opu
Opu
Pin Function
Test Enable
For normal operation, 1K ohm pull-down this pin-to-ground.
Scan Test Scan Mux Enable
For normal operation, 1K ohm pull-down this pin-to-ground.
Port 1 and Port 2 LED indicators
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27. P2LED3 is pin 22.
Digital ground
3.3V digital V
Ready Return Not
For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the
host doesn’t connect to this pin, assert this pin.
For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
DATA Chip Select Not (For KSZ8862-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
When DATACSN is Low, the data path can be accessed regardless of the value of AEN,
A15-A1, and the content of the BANK select register.
No connect.
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend
accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal is
synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8862M drives this pin low to signal wait states.
P1LED3
P1LED2/P2LED2
P1LED1/P2LED1
P1LED0/P2LED0
P1LED3
P1LED2/P2LED2
P1LED1/P2LED1
P1LED0/P2LED0
2
2
/P2LED3
/P2LED3
DDIO
input power supply for IO with well decoupling capacitors.
18
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
—
Link/Act
Full duplex/Col
Speed
Reg. SGCR5 bit [15,9]
[1,0]
Act
Link
Full duplex/Col
Speed
1
defined as follows:
[0,1]
—
10Link/Act
[1,1]
—
—
—
—
100Link/Act
Full duplex
KSZ8862-16/32MQL
M9999-081310-3.1